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| 3dnand-case.md [2026/05/18 14:47] – [Intro] gauthier.roussilhe.ext | 3dnand-case.md [2026/05/18 16:59] (current) – [Variable steps] gauthier.roussilhe.ext | ||
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| 3D NAND refers to a type of non-volatile memory (NVM) used globally for data storage (SD cards, SSDs). These devices have a shorter data access time, consume less power, and are more reliable than HDDs due to the absence of moving parts. A flash memory cell is similar to an NMOS transistor: it has a p-well and an n+ source and drain. However, these cells also have a floating gate (FG), a control gate (CG) and an inter-gate dielectric (IGD). The floating gate acts as a charge trap device that prevents electrons from being discharged via the drain. The memory can be erased by discharging the electrons trapped by the IGD to the CG, causing dielectric breakdown. This explains the write and erase limits of these devices. | 3D NAND refers to a type of non-volatile memory (NVM) used globally for data storage (SD cards, SSDs). These devices have a shorter data access time, consume less power, and are more reliable than HDDs due to the absence of moving parts. A flash memory cell is similar to an NMOS transistor: it has a p-well and an n+ source and drain. However, these cells also have a floating gate (FG), a control gate (CG) and an inter-gate dielectric (IGD). The floating gate acts as a charge trap device that prevents electrons from being discharged via the drain. The memory can be erased by discharging the electrons trapped by the IGD to the CG, causing dielectric breakdown. This explains the write and erase limits of these devices. | ||
| - | < | + | <figure |Flash_memory_cell> |
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| - | < | + | < |
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| * Oxide CVD | * Oxide CVD | ||
| * Oxide CMP | * Oxide CMP | ||
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| ### 3D NAND channel formation process steps | ### 3D NAND channel formation process steps | ||
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| * PolySi CMP | * PolySi CMP | ||
| * Post-CMP clean | * Post-CMP clean | ||
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| ### Process steps for the isolation module of 3D-NAND | ### Process steps for the isolation module of 3D-NAND | ||
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| * W CMP | * W CMP | ||
| * Oxide cap deposition | * Oxide cap deposition | ||
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| + | |||
| ### Process steps of the contact and interconnect module of 3D-NAND | ### Process steps of the contact and interconnect module of 3D-NAND | ||
| * Wafer clean | * Wafer clean | ||
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| t | t | ||
| ## Process steps count | ## Process steps count | ||
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| ### Fixed steps | ### Fixed steps | ||
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| ### Variable steps | ### Variable steps | ||
| - | The total number of process steps depends of the number of layers on the 3D NAND die. Each layer adds 4 process steps (LELE). The repeating steps for each layer are: | + | The total number of process steps depends of the number of layers on the 3D NAND die. Each layer adds 6 process steps (ONON). The repeating steps for each layer are: |
| * x | * x | ||
| * x | * x | ||
| * x | * x | ||
| * x | * x | ||