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back-end.md [2026/05/06 16:21] – [Processes] yusufabdillahback-end.md [2026/05/06 17:29] (current) – [Processes] yusufabdillah
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 ## 1. Wafer thinning ## 1. Wafer thinning
  
 +The wafer thinning process is essential for reducing the overall thickness of the silicon substrate to meet the requirements of modern, ultra-thin portable electronics.
 ### Processes ### Processes
  
 #### 1.1. First optical inspection #### 1.1. First optical inspection
  
-- Electricity+Before thinning, wafers undergo rigorous optical inspection to identify surface defects, particles, or structural anomalies like bubble inclusions that could cause failure. This step ensures that only high-quality wafers proceed to mechanical processing, preventing yield loss from pre-existing hidden voids. Automated scanners use laser light scattering to detect microscopic particles as small as 90 nm. These inspections characterize parameters like bow, warp, and total thickness variation (TTV). The data collected serves as a baseline for measuring material removal accuracy in subsequent steps.
  
-*Expliquer le process First optical inspection : 5-10 lignes*+- Electricity
  
 #### 1.2. Taping #### 1.2. Taping
 +
 +To protect the delicate integrated circuits on the active front side during mechanical thinning, a protective tape is applied. This tape acts as a buffer against mechanical stress and prevents contamination from the slurry or debris generated during grinding. Recent trends have seen an increase in the use of UV-sensitive tapes, which provide high adhesion during processing but can be easily removed later. The tape must be applied uniformly to avoid inducing asymmetric stress that could lead to wafer bowing. For MEMS devices with exposed membranes, specialized tapes with recessed areas may be used to avoid physical contact with fragile structures.
  
 - Electricity - Electricity
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 #### 1.3. Grinding #### 1.3. Grinding
 +
 +Mechanical back-grinding is the primary method for bulk material removal, often utilizing diamond tools to achieve high precision. The process typically involves two stages: rough grinding for rapid removal and fine grinding to achieve the final target thickness. High-precision grinders can routinely achieve a thickness tolerance better than 0.5 µm and minimal subsurface damage. After grinding, chemical-mechanical polishing (CMP) is often employed to remove the final layers of mechanical damage and achieve a mirror-like finish. This thinning is critical for technologies like Through-Silicon Vias (TSVs) and 3D chip stacking.
  
 - Electricity - Electricity
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 - Air - Air
 - Exhaust - Exhaust
 +
 +----
  
 ### Manufacturers ### Manufacturers
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 #### 2.2. Polyimide Spin coating #### 2.2. Polyimide Spin coating
  
-Polyimide is a common dielectric material used in wafer bumping because it provides electrical insulation, with mechanical stress relief, and protection between the redistribution layer and the bump structure. Spin coating works by dispensing liquid polyimide precursor onto the wafer surface (RDL) followed by centrifugal force spreads the film. This dielectric layer also helps to relieve stress between silicon and the underbump metallization (UBM). A good polyimide coating needs to be uniform across the wafer, because thickness variation can cause problems via depth, stress, warpage, and bump height.+Polyimide spin coating refers to the method by which a homogeneous insulating or passivating layer of polyimide can be applied on the wafer. In this step, a small quantity of the liquid form of polyimide resin is dispensed at the center of a spinning silicon wafer. Under centrifugal action, the resin gets distributed towards the edges, where the speed of rotation, viscosity, and temperature dictate the thickness of the deposited film. At this point, there is usually formation of an edge bead on the wafer edges as a result of solvent evaporation, which then removed using a solvent spray (EBR). Polyimides are preferred in bumping because of their flexibility, heat resistance, and stress-buffer capabilities [([[https://www.sciencedirect.com/book/edited-volume/9780128177860/handbook-of-silicon-based-mems-materials-and-technologies|Handbook of silicon based MEMS materials and technologies]], Tilli, Markku, et al., eds. Elsevier, 2020)].
  
 Input Input
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 - Spent solvent - Spent solvent
 - Wastewater - Wastewater
 +
 +----
  
 #### 2.3. Polyimide Photolithography #### 2.3. Polyimide Photolithography
  
-When a polyimide is photoactive, it can be patterned directly with photolithography to form vias and openings through the dielectric material. If the polyimide is not photoactive, then a separate photoresist mask will be used to pattern the polyimide after it is coated and pre-baked. The goal is to expose parts of the seed layer or pad underneath for bump formation while leaving the rest of the wafer insulated and providing mechanical support. Proper alignment of the openings is critical because they must match the pad or redistribution features with good overlay, especially for fine-pitch wafers.+The photolithography technique involves defining locations on the polyimide film where openings are going to be etched. The wafer, which by now has been coated with a photosensitive polyimide film, is accurately positioned beneath a photomask bearing the layout using specialized equipment referred to as a stepper. An ultraviolet (UV) beam of light falls on the mask causing chemical modifications in the exposed parts of the polyimide film. Since polyimide often functions as a negative photoresist, the exposed regions become cross-linked and insoluble, while the unexposed areas remain dissolvable. Important factors for this stage include resolution, sensitivity, and alignment; otherwise, one might have lithography "hotspots," which will destroy any chance of establishing connections [([[https://link.springer.com/referencework/10.1007/978-981-99-2836-1|Handbook of Integrated Circuit Industry]], Wang, Yangyuan, et al., eds. Springer Nature, 2023)].
  
 Input Input
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 - Rinse wastewater - Rinse wastewater
 - Spent mask - Spent mask
 +
 +----
  
 #### 2.4. Polyimide Development #### 2.4. Polyimide Development
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 - Wastewater - Wastewater
 - Chemical waste - Chemical waste
 +
 +----
  
 #### 2.5. Polyimide Curing #### 2.5. Polyimide Curing
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 - Cured polyimide dielectric - Cured polyimide dielectric
 - Outgassed volatiles - Outgassed volatiles
 +
 +----
  
 #### 2.6. Seed layer deposition (PVD) #### 2.6. Seed layer deposition (PVD)
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 - Thin conductive seed film - Thin conductive seed film
 - Heat - Heat
 +
 +----
  
 #### 2.7. Spin coating #### 2.7. Spin coating
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 - Uniform resist film - Uniform resist film
 - Solvent vapor - Solvent vapor
 +
 +----
  
 #### 2.8. Photolithography #### 2.8. Photolithography
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 - Exposed resist pattern - Exposed resist pattern
 +
 +----
  
 #### 2.9. Development & soft baking #### 2.9. Development & soft baking
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 - Plating mold with openings - Plating mold with openings
 - Developer waste - Developer waste
 +
 +----
  
 #### 2.10. Plasma cleaning #### 2.10. Plasma cleaning
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 - Activated/cleaned plating surface - Activated/cleaned plating surface
 - Exhaust gases - Exhaust gases
 +
 +----
  
 #### 2.11. Copper plating #### 2.11. Copper plating
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 - Wastewater - Wastewater
 - Heat - Heat
 +
 +----
  
 #### 2.12. Resin stripping #### 2.12. Resin stripping
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 - Chemical waste - Chemical waste
 - VOCs - VOCs
 +
 +----
  
 #### 2.13. Wet etching #### 2.13. Wet etching
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 - Etched seed/metal waste in solution - Etched seed/metal waste in solution
 - Spent etchant - Spent etchant
 +
 +----
  
 #### 2.14. Bump reflow #### 2.14. Bump reflow