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| cmos_manufacturing [2026/07/16 14:47] – antoine | cmos_manufacturing [2026/07/16 15:00] (current) – [Cu-Cu hybrid bonding] antoine | ||
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| ==== Cu-Cu hybrid bonding ==== | ==== Cu-Cu hybrid bonding ==== | ||
| + | //the Cu-Cu bonding process [13], [14] begins with the parallel preparation of wafers Fig. 17(a). A thick dielectric layer is formed on the silicon using the chemical vapor deposition (CVD). CVD is the process of depositing a solid material in vapor form to achieve uniform thickness throughout the surface. Then, the trench and via which are part of the BEOL | ||
| + | are made. Using the physical vapor deposition (PVD) method, copper seeds are formed in the trench. Following PVD, the | ||
| + | trenches are filled with copper using the electro-chemical deposition (ECD). The excess copper is removed and very low dielectric roughness is attained by chemical mechanical polishing (CMP). Recessing of copper to a certain level is expected during CMP. As seen in 17 (b), the plasma activated wafers are brought together face-to-face and the dielectrics | ||
| + | are bonded instantaneously. After CMP, annealing is done at 150°C to 300°C, due to which the metal expands to fill the gap between them. The aforementioned steps confirm that Cu-Cu hybrid bonding provides physical and electrical connections | ||
| + | due to the dielectric and metal bonding between the substrates.// | ||