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cmos_manufacturing [2026/09/16 11:00] – [8.Packaging and test (TBD)] antoinecmos_manufacturing [2026/09/25 11:03] (current) – [5.Microlens formation] mathieu.ludden.ext
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 Direct methods do not require fabricating a mask or a mold insert containing 3D concave microstructures. The geometry of the lens is established directly, typically exploiting surface tension while the material is in a liquid or thermoplastic state, producing a super smooth surface finish with an arithmetic average roughnes $R_a < 1\text{ nm}$. Direct methods do not require fabricating a mask or a mold insert containing 3D concave microstructures. The geometry of the lens is established directly, typically exploiting surface tension while the material is in a liquid or thermoplastic state, producing a super smooth surface finish with an arithmetic average roughnes $R_a < 1\text{ nm}$.
-  *  Thermal Reflow Method: A photoresist layer is coated onto a substrate and exposed to UV light through a mask with circular array patterns. After development, isolated cylindrical photoresist structures are formed3. Heating these structures causes them to melt and form spherical microlenses due to surface tension. This photolithography and reflow bake approach is a standard MEMS process used for CMOS image sensors.+  *  **Thermal Reflow Method**: A photoresist layer is coated onto a substrate and exposed to UV light through a mask with circular array patterns. After development, isolated cylindrical photoresist structures are formed3. Heating these structures causes them to melt and form spherical microlenses due to surface tension. **This photolithography and reflow bake approach is a standard MEMS process used for CMOS image sensors.**
   * Microplastic Hot Embossing: A silicon mold insert featuring circular openings is first fabricated using deep reactive ion etching (DRIE). A polymer substrate is placed between heating plates and the mold insert, where external pressure is applied above the material's glass transition point to form the microlenses through partial filling. The substrate is then cooled as slowly as possible to reduce thermal stress and replication errors.   * Microplastic Hot Embossing: A silicon mold insert featuring circular openings is first fabricated using deep reactive ion etching (DRIE). A polymer substrate is placed between heating plates and the mold insert, where external pressure is applied above the material's glass transition point to form the microlenses through partial filling. The substrate is then cooled as slowly as possible to reduce thermal stress and replication errors.
   * Microdroplet Jetting (Inkjet Printing): Droplets of a UV-polymerizable liquid are ejected from a nozzle onto a substrate. Upon reaching the substrate, they are exposed to UV light, solidifying into smooth spherical shapes   * Microdroplet Jetting (Inkjet Printing): Droplets of a UV-polymerizable liquid are ejected from a nozzle onto a substrate. Upon reaching the substrate, they are exposed to UV light, solidifying into smooth spherical shapes
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-### 1. Substrate Selection & Frontside Processing (FEOL / BEOL) +====== BSI CMOS Image Sensor Fabrication Process ======
-  * **Starting Substrate**: Fabrication begins on a low-cost bulk silicon wafer (\\(\text{p}/\text{p}^+\\)) or a Silicon-on-Insulator (SOI) wafer. +
-  * **Pinned Photodiode (PPD) Integration**: An \\(\text{n}\\)-type photodiode (\\(\text{nPD}\\)) is implanted inside a \\(\text{p-Epi}\\) layer, covered by a shallow, highly doped surface \\(\text{p}^+\\) pinning layer at the front silicon surface. This PPD structure completely depletes the diode, shields interface defects to suppress dark current, and enables Correlated Double Sampling (CDS) to eliminate reset \\(\text{kTC}\\) noise. +
-  * **Transistor & BEOL Fabrication**: Frontside pixel transistors are patterned—including the Transfer Gate (\\(\text{TG}\\)), Floating Diffusion (\\(\text{FD}\\)), Reset Transistor (\\(\text{RST}\\)), Source Follower (\\(\text{SF}\\)), and Row Select (\\(\text{RS}\\))—followed by standard Back-End of Line (\\(\text{BEOL}\\)) multi-layer metal interconnects.+
  
----+===== 1. Substrate Selection & Frontside Processing (FEOL / BEOL) =====
  
-### 2. Wafer-Level Stacking & Direct / Hybrid Bonding +  * **Starting Substrate**: Fabrication begins on a low-cost bulk silicon wafer (p/p<sup>+</sup>) or a Silicon-on-Insulator (SOI) wafer. 
-  * **Surface Planarization**: Chemical-Mechanical Polishing (\\(\text{CMP}\\)) planarizes the frontside dielectric surface to achieve an ultra-smooth finish with a surface roughness \\(< 0.5\text{ nm}\\). +  * **Pinned Photodiode (PPD) Integration**: An n-type photodiode (nPD) is implanted inside a p-Epi layer, covered by a shallow, highly doped surface p<sup>+</sup> pinning layer at the front silicon surface. This PPD structure completely depletes the diode, shields interface defects to suppress dark current, and enables Correlated Double Sampling (CDS) to eliminate reset kTC noise. 
-  * **Wafer Stacking**: The sensor wafer is flipped face-down and bonded to an ASIC circuit wafer or handle substrate. Stacking is accomplished via low-temperature direct dielectric bonding or \\(\text{Cu/dielectric}\\) Hybrid Bonding (\\(\text{HB}\\)), which directly connects fine-pitch electrical contacts across the bonding interface.+  * **Transistor & BEOL Fabrication**: Frontside pixel transistors are patterned—including the Transfer Gate (TG), Floating Diffusion (FD), Reset Transistor (RST), Source Follower (SF), and Row Select (RS)—followed by standard Back-End of Line (BEOL) multi-layer metal interconnects.
  
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 + 
 +===== 2. Wafer-Level Stacking & Direct / Hybrid Bonding ===== 
 + 
 +  * **Surface Planarization**: Chemical-Mechanical Polishing (CMP) planarizes the frontside dielectric surface to achieve an ultra-smooth finish with a surface roughness < 0.5 nm. 
 +  * **Wafer Stacking**: The sensor wafer is flipped face-down and bonded to an ASIC circuit wafer or handle substrate. Stacking is accomplished via low-temperature direct dielectric bonding or Cu/dielectric Hybrid Bonding (HB), which directly connects fine-pitch electrical contacts across the bonding interface. 
 + 
 +---- 
 + 
 +===== 3. Backside Substrate Thinning =====
  
-### 3. Backside Substrate Thinning 
   * **Mechanical Backgrind**: Mechanical grinding rapidly removes the bulk of the silicon substrate from the backside of the sensor wafer.   * **Mechanical Backgrind**: Mechanical grinding rapidly removes the bulk of the silicon substrate from the backside of the sensor wafer.
-  * **Selective Wet Etching**: Chemical wet etching removes the remaining \\(\text{p}^+\\) substrate and selectively stops at the \\(\text{p-Epi}\\) boundary (or the \\(\text{BOX}\\) oxide interface in SOI wafers). This leaves a thin, highly uniform active silicon layer typically **\\(2\text{ to }4\ \mu\text{m}\\) thick for visible light** or up to **\\(6\ \mu\text{m}\\) for near-infrared (\\(\text{NIR}\\)) sensing**.+  * **Selective Wet Etching**: Chemical wet etching removes the remaining p<sup>+</sup> substrate and selectively stops at the p-Epi boundary (or the BOX oxide interface in SOI wafers). This leaves a thin, highly uniform active silicon layer typically **2 to 4 µm thick for visible light** or up to **6 µm for near-infrared (NIR) sensing**.
  
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 + 
 +===== 4. Backside Isolation & Interface Passivation =====
  
-### 4. Backside Isolation & Interface Passivation 
   * **Backside Deep Trench Isolation (BDTI)**: High-aspect-ratio deep trenches are etched from the backside between individual pixels to eliminate optical and electrical crosstalk.   * **Backside Deep Trench Isolation (BDTI)**: High-aspect-ratio deep trenches are etched from the backside between individual pixels to eliminate optical and electrical crosstalk.
-  * **Defect Passivation via High-\\(k\\) Films**: Atomic Layer Deposition (\\(\text{ALD}\\)) deposits a high-\\(k\\) dielectric stack (such as \\(\text{Al}_2\text{O}_3\\), \\(\text{HfO}_2\\), or \\(\text{Ta}_2\text{O}_5\\)) or performs backside \\(\text{p}^+\\) ion implantation with laser annealing. The negative fixed charges inside the high-\\(k\\) film attract free holes to the trench/silicon interface, forming an induced \\(\text{p}^+\\) accumulation layer that passivates trap defects and repels photogenerated electrons away from surface recombination sites. +  * **Defect Passivation via High-k Films**: Atomic Layer Deposition (ALD) deposits a high-k dielectric stack (such as Al<sub>2</sub>O<sub>3</sub>, HfO<sub>2</sub>, or Ta<sub>2</sub>O<sub>5</sub>) or performs backside p<sup>+</sup> ion implantation with laser annealing. The negative fixed charges inside the high-k film attract free holes to the trench/silicon interface, forming an induced p<sup>+</sup> accumulation layer that passivates trap defects and repels photogenerated electrons away from surface recombination sites. 
-  * **Gap-Fill & Optical Grids**: Trenches are filled with low-stress \\(\text{PECVD}\\) oxide, planarized by \\(\text{CMP}\\), and capped with patterned backside metal grids (e.g., tungsten) to restrict optical light leakage. Optional microscopic pyramid arrays may be etched into the surface to induce total internal reflection and boost quantum efficiency (\\(\text{QE}\\)).+  * **Gap-Fill & Optical Grids**: Trenches are filled with low-stress PECVD oxide, planarized by CMP, and capped with patterned backside metal grids (e.g., tungsten) to restrict optical light leakage. Optional microscopic pyramid arrays may be etched into the surface to induce total internal reflection and boost quantum efficiency (QE).
  
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 + 
 +===== 5. Backside Optical Integration & Packaging =====
  
-### 5. Backside Optical Integration & Packaging +  * **Anti-Reflection Coating (ARC) & Metal Shielding**: A backside ARC layer is deposited to minimize reflection losses, and local backside metal light shields are patterned to protect non-photosensitive areas. 
-  * **Anti-Reflection Coating (ARC) & Metal Shielding**: A backside \\(\text{ARC}\\) layer is deposited to minimize reflection losses, and local backside metal light shields are patterned to protect non-photosensitive areas. +  * **Color Filter Array (CFA)**: Organic primary color filters (e.g., Bayer RGGB pattern) are lithographically aligned and patterned directly on the thinned backside surface.
-  * **Color Filter Array (CFA)**: Organic primary color filters (e.g., Bayer \\(\text{RGGB}\\) pattern) are lithographically aligned and patterned directly on the thinned backside surface.+
   * **Microlens Array Alignment**: Microlenses are fabricated directly over each color filter pixel—commonly using photolithography followed by a thermal reflow bake—to focus incident photons through the short optical stack onto the buried photodiodes.   * **Microlens Array Alignment**: Microlenses are fabricated directly over each color filter pixel—commonly using photolithography followed by a thermal reflow bake—to focus incident photons through the short optical stack onto the buried photodiodes.
-  * **Bond Pad Etching**: Through-Silicon Vias (\\(\text{TSVs}\\)) or bond pad openings are etched through the residual silicon substrate to expose electrical contacts for final packaging (\\(\text{CLCC}\\), \\(\text{CSP}\\), or \\(\text{TSV}\\)-based CameraCube).+  * **Bond Pad Etching**: Through-Silicon Vias (TSVs) or bond pad openings are etched through the residual silicon substrate to expose electrical contacts for final packaging (CLCC, CSP, or TSV-based CameraCube).
  
 ==== Through SIlicon Vias (TSV) ==== ==== Through SIlicon Vias (TSV) ====