Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
intro_cmos [2026/06/30 11:41] – [Complementary Metal-Oxide-Semiconductor (CMOS) Image Sensor] antoineintro_cmos [2026/06/30 13:23] (current) – [Potential well] mathieu.ludden.ext
Line 49: Line 49:
 The pinned photodiode has a p<sup>+</sup>/n-well/p-sub architecture, with a 4T pixel structure. The pinned photodiode has a p<sup>+</sup>/n-well/p-sub architecture, with a 4T pixel structure.
 ==== Potential well==== ==== Potential well====
 +The potential well in a CMOS image sensor is the electron storage region formed inside the N-type pinned photodiode. The combination of the N photodiode and the shallow P+ pinning layer creates a controlled electrostatic minimum that stores photoelectrons with low noise and allows efficient transfer during readout. This structure is the foundation of essentially all modern CMOS image sensors. 
 +
 +The potential well will determine key sensor of the CMOS image sensor such as the Full Well Capacity (FWC), the Charge Transfer Efficiency (CTE), the dark current, the dynamic range, etc.[(Measurement_of_charge_transfer_potential_barrier_in_pinned_photodiode_CMOS_image_sensors > [[https://www.jos.ac.cn/article/doi/10.1088/1674-4926/37/5/054007 | Chen Cao, Bing Zhang, Junfeng Wang and Longsheng Wu Measurement of charge transfer potential barrier in pinned photodiode CMOSimage sensors 2016]])]
  
 ===== Working Principle ===== ===== Working Principle =====