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intro_cmos [2026/08/11 09:38] – [Potential well] xhoana.likmeta.extintro_cmos [2026/09/22 14:18] (current) – [Front side illmunation (FSI) and Bask side illumination (BI)] antoine
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-**2 main technologies: N-Well and P-Well**+==== 2 main technologies: N-Well and P-Well==== 
  
-N-Well:  +**//N-Well Finished structure ://** 
-  * is based on P-type silicon substrate +NMOS sits on the P-substrate (left, blue region) 
-  * N-type impurities diffused in → forms N-well +PMOS sits inside the N-well (right, pink region) 
-  * PMOS transistor built inside the N-well +Every terminal : Body, Source, Gate, Drain - is labeled 
-  * NMOS transistor built directly on the P-substrate +NMOS + PMOS together form one CMOS pair
-  * Most widely used in industry — simpler, well-understood+
  
-<figure center |N-Well process> +<figure center |N-Well finished structure> 
-{{::{{:image4.png?400| https://link.springer.com/chapter/10.1007/978-3-030-79827-7_1}} +{{{{:nwellfinishedstructure.png?400|}} 
-<caption>N-Well +<caption>N-Well finished structure [(N-Well> [[https://link.springer.com/chapter/10.1007/978-3-030-79827-7_1 |Lilak, A.D., Keys, P.H. (2023).  CMOS Manufacturing Processes. In: Rudan, M., Brunetti, R., Reggiani, S. (eds) Springer Handbook of Semiconductor Devices.]])] </caption>
 </figure> </figure>
  
-P-Well: +**//P-Well Finished structure://** 
-  * Base wafer: N-type silicon substrate + PMOS (p+) sits on the N-substrate (dark blue) 
-  * P-type impurities diffused in → forms P-well +NMOS (n+) sits inside the P-well (light blue, right) 
-  * NMOS transistor built inside the P-well +Metal on top connects source, drain, and gate 
-  * PMOS transistor built directly on the N-substrate +Mirror of the N-well structure — polarity swapped
-  * Exact mirror image of the N-well process+
  
-<figure center | P-Well process> +<figure center |P-Well finished structure> 
-{{:{{:image5.png?400| https://link.springer.com/chapter/10.1007/978-3-030-79827-7_1}} +{{{:pwellfinishedstructure.png?400|}} 
-<caption>P-Well +<caption>P-Well Finished structure [(P-Well> [[https://link.springer.com/chapter/10.1007/978-3-030-79827-7_1 |Lilak, A.D., Keys, P.H. (2023).  CMOS Manufacturing Processes. In: Rudan, M., Brunetti, R., Reggiani, S. (eds) Springer Handbook of Semiconductor Devices.]])] </caption>
 </figure> </figure>
- 
- 
- 
  
  
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 <caption> Three CMOS pixel architectures  [(A Review of Optical Sensors in CMOS)]</caption> <caption> Three CMOS pixel architectures  [(A Review of Optical Sensors in CMOS)]</caption>
 </figure> </figure>
-==== Passive pixel sensor (PPS)==== +==== Passive pixel sensor (PPS)=== 
- +//Passive Pixel Sensor (PPS)// is a basic CMOS image sensor pixel architecture. Is an early type of digital image sensor. Each pixel uses a photodiode and a single transistor switch to transfer charges without in-pixel amplification. 
-**Passive Pixel Sensor (PPS)** is a basic CMOS image sensor pixel architecture. Is an early type of digital image sensor. Each pixel uses a photodiode and a single transistor switch to transfer charges without in-pixel amplification. +
 ==== Active pixel sensor (APS)  ==== ==== Active pixel sensor (APS)  ====
-**Active Pixel Sensor (APS):** Each pixel includes active components, typically an amplifier, enabling local charge-to-voltage conversion and multiplexed readout+//Active Pixel Sensor (APS)//:Each pixel includes active components, typically an amplifier, enabling local charge-to-voltage conversion and multiplexed readout
  
-**3T-APS: ** pixel normally contains a photodiode and three transistors: a reset transistor, a source-follower amplifier, and a row/pixel selection transistor.+//3T-APS//: pixel normally contains a photodiode and three transistors: a reset transistor, a source-follower amplifier, and a row/pixel selection transistor.
 It operates through three phases  It operates through three phases 
 1. Reset transistor  1. Reset transistor 
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 4. Photodiode as the light-sensitive element  4. Photodiode as the light-sensitive element 
  
-**4T-APS** adds a transfer gate and uses a pinned (buried) photodiode instead of a basic p-n junction photodiode.+//4T-APS// adds a transfer gate and uses a pinned (buried) photodiode instead of a basic p-n junction photodiode.
 adds one extra transistor compared with 3T APS: adds one extra transistor compared with 3T APS:
 1. Reset transistor  1. Reset transistor 
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 </figure> </figure>
 ====  Digital pixel sensor (DPS) ==== ====  Digital pixel sensor (DPS) ====
- +//Digital Pixel Sensor (DPS)// is a CMOS pixel architecture in which analog-to-digital conversion is performed at the pixel level. 
-Digital Pixel Sensor (DPS) is a CMOS pixel architecture in which analog-to-digital conversion is performed at the pixel level. +
 Each pixel contains a dedicated analog-to-digital converter controlled by reset and select signals. Instead of sending an analog voltage to column circuitry for later conversion, each pixel outputs a digital signal.  Each pixel contains a dedicated analog-to-digital converter controlled by reset and select signals. Instead of sending an analog voltage to column circuitry for later conversion, each pixel outputs a digital signal. 
 ===== Types of illumination ===== ===== Types of illumination =====
  
-==== Front side illmunation (FSI) and Bask side illumination (BI) ====+==== Front side illmunation (FSI) and Back side illumination (BI) ====
 More for early sensors [(Advances_on_CMOS)] More for early sensors [(Advances_on_CMOS)]
 Since its invention in 1993, CMOS image technology has evolved. The first architectures were front-illuminated, meaning the microlens and color filter were on top, followed by metal wiring for interconnects and the photodiode on the bottom. Since light enters the image sensor through the metal layers, some light information is reflected and lost before reaching the photodiode. This affected the performance of front-illuminated sensors, but Sony Corporation solved the problem by moving the photodiode to the top, next to the color filter. This architecture is known as the back-illuminated (BI) CMOS image sensor, which greatly improved the sensor’s performance.  Since its invention in 1993, CMOS image technology has evolved. The first architectures were front-illuminated, meaning the microlens and color filter were on top, followed by metal wiring for interconnects and the photodiode on the bottom. Since light enters the image sensor through the metal layers, some light information is reflected and lost before reaching the photodiode. This affected the performance of front-illuminated sensors, but Sony Corporation solved the problem by moving the photodiode to the top, next to the color filter. This architecture is known as the back-illuminated (BI) CMOS image sensor, which greatly improved the sensor’s performance. 
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 //In the most common **Bayer pattern**, the filters are arranged as (RGGB)  //red, green, green, and blue in a 2 × 2 unit//. In each color “pixel” consists of a 2-by-2 array of photo-detectors where two are designated to green channel and each of the other two are for the blue  //In the most common **Bayer pattern**, the filters are arranged as (RGGB)  //red, green, green, and blue in a 2 × 2 unit//. In each color “pixel” consists of a 2-by-2 array of photo-detectors where two are designated to green channel and each of the other two are for the blue 
-and red channels, as shown in figure 4.+and red channels.
  
 <figure center |color_pattern> <figure center |color_pattern>
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 <figure center | RGB CFA layouts> <figure center | RGB CFA layouts>
-{{ ::{{:doc2_page-0001.jpg?600|}} |https://www.researchgate.net/publication/3181278_Color_filter_arrays_design_and_performance_analysis}} +{{ ::{{:doc2_page-0001.jpg?600|}}  
-<caption> Different color patterns [(Color Filter Arrays: Design and Performance Analysis)] </caption>+<caption> Layout of color patterns [(Color Filter Arrays: Design and Performance Analysis)] </caption>
 </figure> </figure>