intro_wafer
Différences
Ci-dessous, les différences entre deux révisions de la page.
| Prochaine révision | Révision précédente | ||
| intro_wafer [2025/11/24 10:10] – créée louise | intro_wafer [2025/12/05 17:03] (Version actuelle) – [What paths/ideas should be explored?] arthur | ||
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| - | ## Introduction | + | ## System definition |
| - | + | ||
| - | ### Definition | + | |
| A silicon wafer is a thin slice of silicon (semiconductor material) that is used in the manufacturing of integrated circuits. | A silicon wafer is a thin slice of silicon (semiconductor material) that is used in the manufacturing of integrated circuits. | ||
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| Wafers are at the basis of many electronic components like RAMs, CPUs, GPUs, SSDs, etc. | Wafers are at the basis of many electronic components like RAMs, CPUs, GPUs, SSDs, etc. | ||
| - | |||
| ### Are they different types and technologies? | ### Are they different types and technologies? | ||
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| Several wafer technologies exist, with the two main types being logic and memory: | Several wafer technologies exist, with the two main types being logic and memory: | ||
| - | * Logic wafers contain the circuits that perform computations, | ||
| - | * Memory wafers contain the circuits that store information, | ||
| - | * Volatile memory: Data is lost when power is turned off, as in RAM. In this case, the internal structure is very similar to that of logic wafers. | ||
| - | * Non-volatile memory: Data is retained even without power, as in NAND flash memory technology used in SSDs. Especially for 3D NAND, the structure is more vertical and significantly different from that of logic wafers. The processing steps also differ. | ||
| + | * **Logic wafers** contain the circuits that perform computations, | ||
| + | * **Memory wafers** contain the circuits that store information, | ||
| + | * **Volatile memory**: Data is lost when power is turned off, as in RAM. In this case, the internal structure is very similar to that of logic wafers. | ||
| + | * **Non-volatile memory**: Data is retained even without power, as in NAND flash memory technology used in SSDs. Especially for 3D NAND, the structure is more vertical and significantly different from that of logic wafers. The processing steps also differ. | ||
| - | ## Manufacturing | ||
| - | ### What is it made of? | + | ## Life Cycle |
| - | A silicon wafer is made from single-crystal silicon, which is derived from high-purity sand. | + | ### Manufacturing |
| - | ### How is it manufactured? | + | #### What is it made of? |
| + | |||
| + | A silicon wafer is made from single-crystal silicon, which is derived from high-purity sand. | ||
| + | |||
| + | #### How is it manufactured? | ||
| The process involves purifying the sand, melting it, and re-crystallizing it into a large, pure silicon ingot (Czochralski process). This ingot is then sliced into thin discs, which are polished to a mirror-like finish to form the wafer. | The process involves purifying the sand, melting it, and re-crystallizing it into a large, pure silicon ingot (Czochralski process). This ingot is then sliced into thin discs, which are polished to a mirror-like finish to form the wafer. | ||
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| * DUV (Deep Ultra-Violet) Lithography: | * DUV (Deep Ultra-Violet) Lithography: | ||
| * EUV (Extreme Ultra-Violet) Lithography: | * EUV (Extreme Ultra-Violet) Lithography: | ||
| + | |||
| The resolution of each photolithography technique directly impacts the achievable node size, with EUV technology leading the way in current semiconductor advancements. | The resolution of each photolithography technique directly impacts the achievable node size, with EUV technology leading the way in current semiconductor advancements. | ||
| + | |||
| * **Etching**: | * **Etching**: | ||
| * **Doping**: Introducing small amounts of charged particles to modify the electrical properties of the wafer surface. Doping is achieved through ion implantation or diffusion, creating regions of p-type or n-type semiconductor material. | * **Doping**: Introducing small amounts of charged particles to modify the electrical properties of the wafer surface. Doping is achieved through ion implantation or diffusion, creating regions of p-type or n-type semiconductor material. | ||
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| See Gauthier' | See Gauthier' | ||
| - | ### Who are the main manufacturers? | + | #### Who are the main manufacturers? |
| For logic wafers: Intel, AMD, Qualcomm. They rely on foundires like TSMC and GlobalFoundries. | For logic wafers: Intel, AMD, Qualcomm. They rely on foundires like TSMC and GlobalFoundries. | ||
| For memory wafers: | For memory wafers: | ||
| + | |||
| * NAND: Samsung, Kioxia, Western Digital | * NAND: Samsung, Kioxia, Western Digital | ||
| * DRAM: Samsung, SK Hynix, Micron Technology | * DRAM: Samsung, SK Hynix, Micron Technology | ||
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| The semiconductor industry is comprised of three main types of companies, each playing a distinct role: | The semiconductor industry is comprised of three main types of companies, each playing a distinct role: | ||
| + | |||
| * IDMs (Integrated Device Manufacturers): | * IDMs (Integrated Device Manufacturers): | ||
| * Fabless Companies: Design and sell chips but outsource manufacturing to foundries. Notable fabless companies are Nvidia, Qualcomm, AMD, Apple, Broadcom, MediaTek, and Marvell Technology Group. | * Fabless Companies: Design and sell chips but outsource manufacturing to foundries. Notable fabless companies are Nvidia, Qualcomm, AMD, Apple, Broadcom, MediaTek, and Marvell Technology Group. | ||
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| TBC | TBC | ||
| + | |||
| ### What are the main environmental impacts associated to the manufacturing processes? | ### What are the main environmental impacts associated to the manufacturing processes? | ||
| The main impacts are: | The main impacts are: | ||
| + | |||
| * The electricity consumption: | * The electricity consumption: | ||
| * The electricity impacts are also linked to the electric mix of the country or geographical region(s) where it is located. | * The electricity impacts are also linked to the electric mix of the country or geographical region(s) where it is located. | ||
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| TBC | TBC | ||
| - | |||
| ### What paths/ideas should be explored? | ### What paths/ideas should be explored? | ||
| * Confront Negaoctet' | * Confront Negaoctet' | ||
| + | * Estimate the environmental impact of the wafer packaging [[categorie: | ||
intro_wafer.1763975403.txt.gz · Dernière modification : de louise
