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--- intro_wafer [2026/05/08 15:17] – [Database and tools] gauthier.roussilhe.ext
+++ intro_wafer [2026/05/13 17:01] (current) – [Database and tools] gauthier.roussilhe.ext
@@ Line 62: / Line 62: @@
 We exclude research and development, chip design (except for photomasks manufacturing) and later stages after chips exit the final production line.
-We also focus on silicon-based chips, excluding de facto germanium, gallium, indium phosphide-based and other substrates that are used for different applications (power electronics, lasers, etc.)
+We also focus on silicon-based chips, excluding de facto germanium, gallium, indium phosphide-based and other substrates that are used for different applications (power electronics, lasers, etc.
+)
 ### Functional unit and reference flows
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 **The functional unit is yet to be determined**.
-Historically, the environmental footprint of integrated circuit manufacturing has been defined by the following UF: the production of cm² / die. This functional unit is calculated by determining the manufacturing footprint of m² of wafer and then accounting for various losses associated with the kerf, defect density, die format and other yield parameters.
+Historically, the environmental footprint of integrated circuit manufacturing has been defined by the following UF: the production of cm²/die. This functional unit is calculated by determining the manufacturing footprint of m² of wafer and then accounting for various losses associated with the kerf, defect density, die format and other yield parameters.
 Other proxies may be used to complement a chip’s manufacturing footprint: the number of manufacturing steps[(Weppe, O., Marty, T., Toussaint, S., Brusselmans, N., Prévotet, J. C., Raskin, J. P., & Pelcat, M. (2025, May). Embodied carbon footprint of 3D NAND memories. In Proceedings of the 22nd ACM International Conference on Computing Frontiers: Workshops and Special Sessions (pp. 108-116).)]; the average environmental footprint of each type of process multiplied by the number of steps per process[(Bardon, M. G., Wuytens, P., Ragnarsson, L. Å., Mirabelli, G., Jang, D., Willems, G., ... & Parvais, B. (2020, December). DTCO including sustainability: Power-performance-area-cost-environmental score (PPACE) analysis for logic technologies. In 2020 IEEE International Electron Devices Meeting (IEDM) (pp. 41-4). IEEE.)]; the average footprint based on a fab’s throughput[(Liu, I. Y., Van Winckel, L., Boakes, L., Bardon, M. G., Rolin, C., & Ragnarsson, L. Å. (2024). Modeling the energy consumption of integrated circuit fab infrastructure. IEEE Transactions on Semiconductor Manufacturing, 37(4), 422-427.)]; or a bottom-up approach for analysts with access to primary data from a fab.
 Recent works also point out that allocation of impacts could differ depending of binning, i.e. differentiation of a lot according to performance, and then implying a price-based and performance-based allocation[(Weppe, O., Marty, T., Prévotet, J. C., & Pelcat, M. (2026, April). Beyond Silicon Area: Co-Product Allocation for a Binning-Aware Carbon Footprint of Processors. In Sustech.)].
+The cm²/die ratio depends entirely on knowing the exact die area, which is not automatically provided by manufacturers. This area is not directly accessible or visible as it is covered by the packaging. Consequently, an inaccurate estimate of the die area can cause significant variations in the footprint of a chip and the equipment that houses it. Proske et al provide a database of die-to-package ratios based on direct measurement or radiographic imaging of 189 chips[(Proske, M., Billaud, M., Clemm, C., Sanchez, D., Lorf, Y., & Stobbe, L. (2024, June). Investigation of semiconductor die area as a reference variable for LCA. In 2024 Electronics Goes Green 2024+(EGG) (pp. 1-5). IEEE.)] to circumvent this issue.
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 #### What are the already existing data (dataset, parametric model, paper, etc.)?
-Pirson et al provide
+Regarding front-end manufacturing, Pirson et al provide a comprehensive review of historical and actual trends regarding environmental impacts of IC production per technology nodes and based on scientific literature and LCA databases[(Pirson, T., Delhaye, T. P., Pip, A. G., Le Brun, G., Raskin, J. P., & Bol, D. (2022). The environmental footprint of IC production: Review, analysis, and lessons from historical trends. IEEE Transactions on Semiconductor Manufacturing, 36(1), 56-67.)].
 <figure right|fig_pirson>
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 </figure>
-Furthermore, several datasets and models already exist, such as:
+Furthermore, several datasets and models already exist from LCA databases such as:
   * [[https://codde.fr/en/our-brands/negaoctet|Negaoctet's dataset]]
-  * [[https://netzero.imec-int.com|imec.netzero app]]
   * [[https://db.resilio.tech/|Resilio's database]]
+  * [[https://ecoquery.ecoinvent.org/3.8/cutoff/dataset/579/documentation|ecoinvent]]
+Several parametric models are also available from industry specialists:
+  * [[https://netzero.imec-int.com|imec.netzero app]]
+  * [[https://www.techinsights.com/solutions/semiconductor-manufacturing-carbon-model|TechInsight's Semiconductor Manufacturing Carbon Module]]
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   * [Back-end manufacturing flow](back-process-flow.md)
   * [Back-end processes](back-end.md)
+  * [3D NAND use case](3dnand-case.md)
+  * [DRAM use case](dram-case.md)