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modelization-strategy.md [2026/06/24 15:00] – [Modelization] gauthier.roussilhe.extmodelization-strategy.md [2026/06/24 16:36] (current) – [How does this approach answer to our objectives?] gauthier.roussilhe.ext
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 A **traveler** provides the sequential list of all the steps a wafer must go through and the areas of the cleanroom to which the wafer must be transported for each step. A traveler provides far less information about the processes and their calibration, but it does indicate the total number of steps and the types of processes involved. A **traveler** provides the sequential list of all the steps a wafer must go through and the areas of the cleanroom to which the wafer must be transported for each step. A traveler provides far less information about the processes and their calibration, but it does indicate the total number of steps and the types of processes involved.
  
-<figure> +<figure center> 
-{{ :wafer-traveler.png?550|}} +{{ :wafer-recipe.webp?800 |}} 
- <caption>Example of a traveler for a memory chip (source: Micron)</caption>+ <caption>Examples of recipe, travelers and steps distribution (source: Micron)</caption>
 </figure> </figure>
- +## Modelization approach
-<figure> +
-{{:wafer-traveler-2.png?550|}} +
- <caption>Example of a traveler for a CMOS device (source: Micron)</caption> +
-</figure> +
- +
-<figure> +
-{{ :wafer-distribution.png?700 |}} +
- <caption>Typical distribution of the number of traveler steps by each functional area for a memory chip (source: Micron)</caption> +
-</figure> +
- +
-## Modelization+
  
 Our approach is based on three key factors: Our approach is based on three key factors:
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   * Average inputs and outputs per process type for one step   * Average inputs and outputs per process type for one step
  
-These parameters are, of course, supplemented by traditional parameters used in this type of assessment, such as: +Our aim is to define archetypes, defining these three factors, for each type of device (logic, DRAM, NAND) and their key characteristics (node size for logic and DRAM, number of layers for NAND). 
-  * device type + 
-  * technology node+These factors are, of course, supplemented by traditional parameters used in this type of assessment, such as:
   * die size   * die size
   * die yield   * die yield
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   * fab overhead   * fab overhead
   * etc.   * etc.
 +
 +
 +<figure center>
 +{{:wafer-model-archetype.webp|800}}
 + <caption>Simplified illustration of the modelization approach</caption>
 +</figure>
 +### How does this approach answer to our objectives?
 +
 +#### Improve existing models
 +This approach provides a more precise quantification than the classic approach based on cm² per die. However, imec.netzero might already follow the same approach [To be discussed]
 +
 +#### Respect trade secrets
 +Our approach, based on averages, aims to respect the trade secrets of manufacturers and laboratories. We don't need the precise total number of steps and the process type distribution, we just need to agree on representative averages (with min, max if possible). Working with average inputs/outputs per process type (CVD, dry etch, photolitho, etc.) allows to share agregate data that doesn't show actual recipes.
 +
 +#### Open/customizable
 +
 +[To be completed]
 +
 +#### Robust/representativeness
 +
 +[To be completed]
 +