This page is read only. You can view the source, but not change it. Ask your administrator if you think this is wrong. ====== CMOS manufacturing ====== ===== Stacked Back-Illuminated CMOS Image Sensor (Bi-CIS) ===== This page focuses on the process of the tacked Back-Illuminated CMOS Image Sensor (BI-CIS). <figure center |3_layer_pixel_DRAM_CIS> {{ :strcture_3_layer_pixel_dram_cis.png?direct&400 |https://arxiv.org/abs/2306.05339}} <caption>Strcuture of a 3 layers pixel/DRAM/CIS [(review_fabrication_processes_CIS > [[https://arxiv.org/abs/2306.05339 | A Review of the Recent Developments in the Fabrication Processes of CMOS Image Sensors for Smartphones, Kirthika Nahalingam, Linda P. B. Katehi, 2023]])] </caption> </figure> ==== Through SIlicon Vias (TSV) ==== //The process flow of stacking the 3-layer CIS is illustrated in the Fig. 10. The fabrication process begins with the par-allel processing of wafers where each wafer is bonded to their respective substrates individually. The DRAM is flipped bonded to the logic substrate face-face. The DRAM substrate is thinned to about 3μm after the bonding. Then, the lower TSVs and the metal wiring connecting both the substrates are formed. Later, the pixel substrate is flipped and bonded to the already stacked DRAM/logic substrate and then the upper TSVs are made to connect the pixel substrate to the rest of the stack// <figure center |process_flow_CIS_TSV> {{ :process_flow_of_3-layer_stacked_cis_using_tsv.png?direct&400 |https://arxiv.org/abs/2306.05339}} <caption>Process flow of 3-layer stacked CIS using TSV [(review_fabrication_processes_CIS)] </caption> </figure> <figure center |cross_section_BI_CIS> {{ ::cross_section_3-layer_stacked_bi-cis_chip.png?direct&400 |https://arxiv.org/abs/2306.05339}} <caption> Cross section of the 3-layer BI-CIS [(review_fabrication_processes_CIS)] </caption> </figure> ==== Cu-Cu hybrid bonding ==== //the Cu-Cu bonding process [13], [14] begins with the parallel preparation of wafers Fig. 17(a). A thick dielectric layer is formed on the silicon using the chemical vapor deposition (CVD). CVD is the process of depositing a solid material in vapor form to achieve uniform thickness throughout the surface. Then, the trench and via which are part of the BEOL are made. Using the physical vapor deposition (PVD) method, copper seeds are formed in the trench. Following PVD, the trenches are filled with copper using the electro-chemical deposition (ECD). The excess copper is removed and very low dielectric roughness is attained by chemical mechanical polishing (CMP). Recessing of copper to a certain level is expected during CMP. As seen in 17 (b), the plasma activated wafers are brought together face-to-face and the dielectrics are bonded instantaneously. After CMP, annealing is done at 150°C to 300°C, due to which the metal expands to fill the gap between them. The aforementioned steps confirm that Cu-Cu hybrid bonding provides physical and electrical connections due to the dielectric and metal bonding between the substrates.//