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# Wafers


## System definition

A silicon wafer is a thin slice of silicon (semiconductor material) that is used in the manufacturing of integrated circuits.  

### What is it used for?

Wafers are at the basis of many electronic components like RAMs, CPUs, GPUs, SSDs, etc.
### Are they different types and technologies?

Yes are many different types of wafers, depending on material, Crystal structure, processing, etc.

Here we focus on the wafers used in electronics : **monocrystalline silicon wafer**.

Several wafer technologies exist, with the two main types being logic and memory:

* **Logic wafers** contain the circuits that perform computations, logical operations, and data processing, for example in CPUs and GPUs. They follow a specific modeling approach.
* **Memory wafers** contain the circuits that store information, either volatile or non-volatile.
  * **Volatile memory**: Data is lost when power is turned off, as in RAM. In this case, the internal structure is very similar to that of logic wafers.
  * **Non-volatile memory**: Data is retained even without power, as in NAND flash memory technology used in SSDs. Especially for 3D NAND, the structure is more vertical and significantly different from that of logic wafers. The processing steps also differ.


## Life Cycle

### Manufacturing

#### What is it made of?

A silicon wafer is made from single-crystal silicon, which is derived from high-purity sand.

#### How is it manufactured?

The process involves purifying the sand, melting it, and re-crystallizing it into a large, pure silicon ingot (Czochralski process). This ingot is then sliced into thin discs, which are polished to a mirror-like finish to form the wafer.

Once the disks are obtained, the main steps are:

* **Wafer Production**: The process begins with creating wafers from pure crystalline silicon. Silicon ingots are sawed into wafers using diamond-coated wire. These wafers, ranging in diameters from 100 mm to 300 mm, are then polished to achieve an even and clean surface, essential for preventing defects and ensuring the integrity of the semiconductor devices.
* **Deposition**: Thin films of materials, typically oxides, are deposited on the wafer. This process can be physical or chemical, creating a mask layer necessary for subsequent patterning steps.
* **Photolithography**: Photolithography is a critical process in defining the intricate patterns of integrated circuits (ICs). It involves applying a photoresist layer to the wafer, which is then exposed to a light source through a photomask to project the desired circuit pattern onto the photoresist. The resolution of this process, determined by the wavelength of the light source, dictates the size of the semiconductor nodes. There are various types of photolithography used in semiconductor manufacturing:
  * DUV (Deep Ultra-Violet) Lithography: Uses KrF (248 nm) for nodes ≥150 nm and ArF (193 nm) in dry (≥65 nm) and immersion forms (≥7 nm).
  * EUV (Extreme Ultra-Violet) Lithography: Employs a 13.5 nm light source, achieving the smallest nodes, such as 5 nm.

The resolution of each photolithography technique directly impacts the achievable node size, with EUV technology leading the way in current semiconductor advancements.

* **Etching**: This step removes parts of the photoresist and oxide layer exposed by the laser, creating the desired patterns on the wafer. Etching can be performed using either dry (plasma-phase) or wet (liquid-phase) techniques.
* **Doping**: Introducing small amounts of charged particles to modify the electrical properties of the wafer surface. Doping is achieved through ion implantation or diffusion, creating regions of p-type or n-type semiconductor material.
* **Stripping**: Removing unwanted photoresist layers from the wafer. This can be done using organic, inorganic, or dry stripping methods.
* **Back-End-of-Line (BEOL) Process**: After front-end-of-line (FEOL) processing, the BEOL process involves depositing metal wiring to interconnect the transistors on the wafer. This process includes additional layers of photoresist application, UV exposure, and etching, adding 5 to 12 more layers to the wafer.
* **Repetition and Layering**: The entire process is repeated 40 to 100 times to build multiple layers necessary for complex integrated circuits.
* **Dicing and Packaging**: Once the wafer processing cycle is complete, the wafer is diced into individual chips. These chips are tested for functionality and then encapsulated in protective packages to prevent physical damage and corrosion.
* **Final Testing**: Ensures the integrity and functionality of the chips post-packaging, verifying that they meet the required specifications before being deployed in electronic devices.

See Gauthier's posters for more details

#### Who are the main manufacturers?

For logic wafers: Intel, AMD, Qualcomm. They rely on foundires like TSMC and GlobalFoundries.
For memory wafers:

* NAND: Samsung, Kioxia, Western Digital
* DRAM: Samsung, SK Hynix, Micron Technology

Source : https://ieeexplore.ieee.org/document/10413715

The semiconductor industry is comprised of three main types of companies, each playing a distinct role:

* IDMs (Integrated Device Manufacturers): Perform all stages from design to manufacturing and sales in-house. Examples include Intel, Texas Instruments, Samsung Electronics, and Micron Technology.
* Fabless Companies: Design and sell chips but outsource manufacturing to foundries. Notable fabless companies are Nvidia, Qualcomm, AMD, Apple, Broadcom, MediaTek, and Marvell Technology Group.
* Foundries: Manufacture wafers based on client designs. Leading foundries are TSMC, UMC, GlobalFoundries, SMIC, and Samsung Foundry.

Additionally, it is increasingly common for IDMs to outsource part of their production to foundries. Some IDMs, like IBM and Samsung, also offer foundry services to fabless companies.


### Where are they located?

The Asia Pacific region is the largest semiconductor industry region, with China as the leading single-country market. Despite a 15% decline since 2021, China's market remains critical. The Americas and Europe show resilience, with Europe's market growing by 4% in 2023. Japan experienced a slight decline, reflecting the competitive nature of the market. These regional dynamics underscore the semiconductor industry's global interconnectedness and sensitivity to geopolitical and economic factors.

Source: https://www.semiconductors.org/wp-content/uploads/2024/05/SIA-2024-Factbook.pdf

The global semiconductor manufacturing industry is highly concentrated in East Asia, the United States, and the European Union with these regions housing over 90% of all facilities. East Asia, with 292 sites, represents around 66% of the total, dominating global chip production. Taiwan alone produces 60% of the world's semiconductors and 90% of the most advanced ones, especially logic chips. Additionally, Korean companies hold a commanding 60% share of the memory chip market. This map visualizes the geographic distribution and processing capabilities of semiconductor manufacturing facilities.

Cutting-edge wafer fabrication, particularly at nodes of 7nm or less, is predominantly found in South Korea and Taiwan. Europe, on the other hand, lacks these advanced facilities and as a consequence lags in adopting more mature technology nodes. A tiny share of wafer capacity for nodes between 10nm to 20nm exists in Europe, mainly due to Intel’s fabs in Ireland and Israel, which are currently not available for contract manufacturing. Furthermore, European fabs like those from STMicroelectronics and GlobalFoundriesoperate nodes from 22nm to 40nm, but the majority of Europe’s capacity (almost 50%) consists of older nodes of 180nm or larger, used extensively for automotive and industrial applications.

Source: https://technologyglobal.substack.com/p/semiconductor-manufacturing-facilities



## Environmental footprint

### What are the main environmental impacts associated to the materials?

TBC


### What are the main environmental impacts associated to the manufacturing processes?

The main impacts are:

* The electricity consumption: Some manufacturing steps are very energy-intensive: deposition, lithography, and etching. The value depends on the technology node (lithography) because the equipment used and the number of steps in the process are not the same.
* The electricity impacts are also linked to the electric mix of the country or geographical region(s) where it is located.
* Process gases: Various gases are used during the process, mostly for chemical vapor deposition and dry etch processes. However, the gases may not be entirely consumed, or gaseous by-products may be generated. Gas abatement techniques are applied, involving cracking the gases into less harmful compounds. The various gas emissions that are considered are the following: SF6, NF3, N2O, CO2, CHF3, CF4, C4F8, C2F6. Gas abatement is generally used in the process to reduce the amount of emitted gases. 
* Water consumption: During wafer processing, a certain amount of water is required. Approximately 76% of this water is used to generate ultra-pure water (UPW), mainly for chemical mechanical planarization and wet cleaning steps. A production yield of 62.5% is assumed. The remaining water is used as is.


### What are the potential parameters affecting environmental impact?

* Device type (logic, DRAM or NAND)
* Diameter of the wafer (mm)
* Surface of the final die (mm2)
* Lithography (nm)
* Yield of the process
* The manufacturing location


### Already existing data? (dataset, parametric model, paper, etc.)

Negaoctet's datasets, imec tool, Resilio's parametric model


##  Next steps

### What do we know we don't know?

* The purity of the silicon crystal is not properly taken into account in the existing LCAs

### What are the identified challenges?

TBC
### What paths/ideas should be explored?

* Confront Negaoctet's datasets and imec results in order to understand what are the reasons for the differences

* Estimate the environmental impact of the wafer packaging [[categorie:page#ici|wafer packaging]]