====== CMOS manufacturing ======

===== Stacked Back-Illuminated CMOS Image Sensor (Bi-CIS) =====

This page focuses on the process of the tacked Back-Illuminated CMOS Image Sensor (BI-CIS). 

<figure center |3_layer_pixel_DRAM_CIS>
{{ :strcture_3_layer_pixel_dram_cis.png?direct&400 |https://arxiv.org/abs/2306.05339}}
<caption>Strcuture of a 3 layers pixel/DRAM/CIS [(review_fabrication_processes_CIS > [[https://arxiv.org/abs/2306.05339 | A Review of the Recent Developments in the Fabrication Processes of CMOS Image Sensors for Smartphones, Kirthika Nahalingam, Linda P. B. Katehi, 2023]])] </caption>
</figure>

===== MANUFACTURING STEPS =====

WORK IN PROGRESS
==== 1. Wafer Preparation ====
Fabrication starts on an epitaxial silicon wafer — a thin, high-purity silicon layer grown on a substrate. The epi layer's thickness and doping are tuned for good light absorption and low crosstalk between neighbouring pixels. The epi thickness has to be thick enough for a good long-wavelength quantum efficiency but thin enough to limit crosstalk and to keep backside thinning practical. The doping purity uniformity of the epi is important to keep metal contamination away from the active photodiode region.

==== 2. Front-end-of-line ====
FEOL for a CMOS image sensor pixel isn't just "build the transistors" — it's building four specific transistors whose job is to convert a tiny packet of collected charge into a clean, readable voltage	: the transfer gate, reset gate, source-follower gate, and row-select gate.

=== 2.1 Well formation ===
P-wells and n-wells are implanted and thermally driven in to set up the regions where the different transistor types will sit, around the photodiode so the well doping doesn't interfere with the light-collecting region or create unwanted leakage paths to it.

=== 2.2.	Shallow trench isolation  ===
Trenches are etched around the pixel's readout transistors, filled with oxide, and polished flat to electrically separate transistors from each other.

=== 2.3.	Gate oxide growth  ===
An extremely thin, uniform oxide layer is grown wherever a transistor channel will form. Its thickness sets the transistor's threshold voltage and switching behavior.

=== 2.4.	Polysilicon gate deposition and patterning  ===
A conductive gate layer is deposited over the oxide, then lithographically patterned and etched to define each transistor's exact gate lengt.

=== 2.5.	Lightly doped drain (LDD) implants  ===
Light dopant regions are added next to most gate edges to soften the electric field at the drain and improve long-term reliability. 
The transfer gate is the exception — its doping profile is engineered differently, with a smoother potential slope rather than a sharp LDD junction, specifically to help charge slide cleanly from the photodiode to the floating diffusion instead of getting trapped partway.

=== 2.6.	Sidewall spacers  ===
A thin dielectric spacer is formed on the sides of each gate.

=== 2.7.	Source/drain implantation ===
Heavier doping forms the actual source and drain terminals of each transistor. The floating diffusion area is lightly doped, because a smaller floating diffusion electrical capacity means more output voltage per electron collected. A metric called conversion gain that directly determines how much read noise shows up in low light.

=== 2.8.	Silicide block  ===
In most logic transistors, a metal silicide is formed on top of the source/drain to cut resistance. Over the photodiode and the floating diffusion, this step is masked off entirely, since silicide formation right next to the light-sensitive node would introduce extra defects and leakage exactly where it matters most.

=== 2.9.	Anneal ===
A final thermal step activates all the implants and repairs the crystal lattice damage from the various implantation steps.

==== 3.	Interconnect formation (back-end-of-line) ====
Multiple layers of metal wiring (copper or aluminum) and dielectric are built up to connect transistors and route signals off the pixel array. In sensors using front-side illumination, this stack sits directly in the light path, so metal routing must be carefully designed to avoid blocking the photodiode.

=== 3.1.	Light shields  ===
A metal layer is often deliberately placed as an opaque block over non-photosensitive structures (the floating diffusion, the transistors, and dedicated "dark" reference pixels used for calibration), preventing stray light from generating unwanted charge there.

=== 3.2.	Global shutter storage shielding (optional)  ===
Sensors with a global shutter need a charge-storage node shielded almost perfectly from light during readout, since even a tiny light leak would corrupt the stored frame with new photo-charge. This can require dedicated extra metal layers with very high shielding effectiveness.

=== 3.3.	Reflective layers  ===
In some BSI designs, a metal layer placed behind the photodiode reflects unabsorbed long-wavelength light back up for a second absorption pass, boosting red/near-infrared sensitivity without needing a thicker silicon layer.

=== 3.4.	Final planarization ===
Because the color filter and microlens sit directly on top of this stack, the last dielectric layer needs to be extremely flat — not just electrically fine, but optically flat across the whole array.

==== 4.	Color filter array deposition (TBD) ====
=== 4.1.	Planarization ===
=== 4.2.	Coat resist ===
=== 4.3.	Photoresist exposure ===
=== 4.4.	Develop ===
=== 4.5.	Cure ===
=== 4.6.	Repeat process for each color ===
=== 4.7.	Overcoat ===
=== 4.8.	Inspect ===

==== 5.	Microlens formation ====
The fabrication methods for microlens arrays are categorized into two primary groups: **direct methods** and **indirect methods** [(fabrication_microlenses_array > [[https://link.springer.com/article/10.1186/s10033-018-0204-y#citeas | Yuan, W., Li, LH., Lee, WB. et al. Fabrication of Microlens Array and Its Application: A Review. Chin. J. Mech. Eng. 31, 16 (2018). https://doi.org/10.1186/s10033-018-0204-y]])] [(microlens_design > [[ https://www.researchgate.net/publication/252221021_Microlens_design_for_CMOS_image_sensor | Microlens design for CMOS image sensor, C.Fossati, 2005]])]

=== Direct methods ===

Direct methods do not require fabricating a mask or a mold insert containing 3D concave microstructures. The geometry of the lens is established directly, typically exploiting surface tension while the material is in a liquid or thermoplastic state, producing a super smooth surface finish with an arithmetic average roughnes $R_a < 1\text{ nm}$.
  *  **Thermal Reflow Method**: A photoresist layer is coated onto a substrate and exposed to UV light through a mask with circular array patterns. After development, isolated cylindrical photoresist structures are formed3. Heating these structures causes them to melt and form spherical microlenses due to surface tension. **This photolithography and reflow bake approach is a standard MEMS process used for CMOS image sensors.**
  * Microplastic Hot Embossing: A silicon mold insert featuring circular openings is first fabricated using deep reactive ion etching (DRIE). A polymer substrate is placed between heating plates and the mold insert, where external pressure is applied above the material's glass transition point to form the microlenses through partial filling. The substrate is then cooled as slowly as possible to reduce thermal stress and replication errors.
  * Microdroplet Jetting (Inkjet Printing): Droplets of a UV-polymerizable liquid are ejected from a nozzle onto a substrate. Upon reaching the substrate, they are exposed to UV light, solidifying into smooth spherical shapes

=== Indirect methods ===

Indirect methods rely on first fabricating a concave mold, from which the final microlens arrays are duplicated using replication techniques such as injection molding, hot embossing, or UV molding. These methods provide precise geometric control. Two main technological approaches are used to manufacture the concave matrices :
  * MEMS-Based Technologies: Standard MEMS processes combine photolithography with chemical etching (such as isotropic wet etching of silicon) to form the concave microcavities.
  * Direct writing techniques, including femtosecond laser wet etching, focused ion beam (FIB) writing, and electron beam writing, can also directly generate concave patterns on the substrate.
  * Ultraprecision Machining Technologies: These processes use single-crystal diamond cutting tools to machine microstructures with high uniformity across large areas. Methods include diamond ball-end milling using half-arc single-crystal tools and Single Point Diamond Turning (SPDT) controlled by a fast tool servo or slow slide servo.

==== 6.	Backside illumination (BSI) processing (TBD) ====
==== 7.	Wafer stacking (for advanced sensors) (TBD) ====
==== 8.	Packaging and test (TBD) ====



===== Process line 2  =====

The complete process line for manufacturing a **Back-Side-Illuminated (BSI) CMOS Image Sensor (CIS)** incorporating a **Pinned Photodiode (PPD)** follows a multi-stage flow combining Front-End/Back-End processing, wafer-level stacking, substrate thinning, and backside optical integration:

---

====== BSI CMOS Image Sensor Fabrication Process ======

===== 1. Substrate Selection & Frontside Processing (FEOL / BEOL) =====

  * **Starting Substrate**: Fabrication begins on a low-cost bulk silicon wafer (p/p<sup>+</sup>) or a Silicon-on-Insulator (SOI) wafer.
  * **Pinned Photodiode (PPD) Integration**: An n-type photodiode (nPD) is implanted inside a p-Epi layer, covered by a shallow, highly doped surface p<sup>+</sup> pinning layer at the front silicon surface. This PPD structure completely depletes the diode, shields interface defects to suppress dark current, and enables Correlated Double Sampling (CDS) to eliminate reset kTC noise.
  * **Transistor & BEOL Fabrication**: Frontside pixel transistors are patterned—including the Transfer Gate (TG), Floating Diffusion (FD), Reset Transistor (RST), Source Follower (SF), and Row Select (RS)—followed by standard Back-End of Line (BEOL) multi-layer metal interconnects.

----

===== 2. Wafer-Level Stacking & Direct / Hybrid Bonding =====

  * **Surface Planarization**: Chemical-Mechanical Polishing (CMP) planarizes the frontside dielectric surface to achieve an ultra-smooth finish with a surface roughness < 0.5 nm.
  * **Wafer Stacking**: The sensor wafer is flipped face-down and bonded to an ASIC circuit wafer or handle substrate. Stacking is accomplished via low-temperature direct dielectric bonding or Cu/dielectric Hybrid Bonding (HB), which directly connects fine-pitch electrical contacts across the bonding interface.

----

===== 3. Backside Substrate Thinning =====

  * **Mechanical Backgrind**: Mechanical grinding rapidly removes the bulk of the silicon substrate from the backside of the sensor wafer.
  * **Selective Wet Etching**: Chemical wet etching removes the remaining p<sup>+</sup> substrate and selectively stops at the p-Epi boundary (or the BOX oxide interface in SOI wafers). This leaves a thin, highly uniform active silicon layer typically **2 to 4 µm thick for visible light** or up to **6 µm for near-infrared (NIR) sensing**.

----

===== 4. Backside Isolation & Interface Passivation =====

  * **Backside Deep Trench Isolation (BDTI)**: High-aspect-ratio deep trenches are etched from the backside between individual pixels to eliminate optical and electrical crosstalk.
  * **Defect Passivation via High-k Films**: Atomic Layer Deposition (ALD) deposits a high-k dielectric stack (such as Al<sub>2</sub>O<sub>3</sub>, HfO<sub>2</sub>, or Ta<sub>2</sub>O<sub>5</sub>) or performs backside p<sup>+</sup> ion implantation with laser annealing. The negative fixed charges inside the high-k film attract free holes to the trench/silicon interface, forming an induced p<sup>+</sup> accumulation layer that passivates trap defects and repels photogenerated electrons away from surface recombination sites.
  * **Gap-Fill & Optical Grids**: Trenches are filled with low-stress PECVD oxide, planarized by CMP, and capped with patterned backside metal grids (e.g., tungsten) to restrict optical light leakage. Optional microscopic pyramid arrays may be etched into the surface to induce total internal reflection and boost quantum efficiency (QE).

----

===== 5. Backside Optical Integration & Packaging =====

  * **Anti-Reflection Coating (ARC) & Metal Shielding**: A backside ARC layer is deposited to minimize reflection losses, and local backside metal light shields are patterned to protect non-photosensitive areas.
  * **Color Filter Array (CFA)**: Organic primary color filters (e.g., Bayer RGGB pattern) are lithographically aligned and patterned directly on the thinned backside surface.
  * **Microlens Array Alignment**: Microlenses are fabricated directly over each color filter pixel—commonly using photolithography followed by a thermal reflow bake—to focus incident photons through the short optical stack onto the buried photodiodes.
  * **Bond Pad Etching**: Through-Silicon Vias (TSVs) or bond pad openings are etched through the residual silicon substrate to expose electrical contacts for final packaging (CLCC, CSP, or TSV-based CameraCube).

==== Through SIlicon Vias (TSV) ====
 
//The process flow of stacking the 3-layer CIS is illustrated in the Fig. 10. The fabrication process begins with the par-allel processing of wafers where each wafer is bonded to their respective substrates individually. The DRAM is flipped bonded to the logic substrate face-face. The DRAM substrate is thinned to about 3μm after the bonding. Then, the lower TSVs and the metal wiring connecting both the substrates are formed. Later, the pixel substrate is flipped and bonded to the already stacked DRAM/logic substrate and then the upper TSVs are made to connect the pixel substrate to the rest of the stack//

<figure center |process_flow_CIS_TSV>
{{ :process_flow_of_3-layer_stacked_cis_using_tsv.png?direct&400 |https://arxiv.org/abs/2306.05339}}
<caption>Process flow of 3-layer stacked CIS using TSV [(review_fabrication_processes_CIS)] </caption>
</figure>

<figure center |cross_section_BI_CIS>
{{ ::cross_section_3-layer_stacked_bi-cis_chip.png?direct&400 |https://arxiv.org/abs/2306.05339}}
<caption> Cross section of the 3-layer BI-CIS [(review_fabrication_processes_CIS)] </caption>
</figure>

==== Cu-Cu hybrid bonding ====

//the Cu-Cu bonding process [13], [14] begins with the parallel preparation of wafers Fig. 17(a). A thick dielectric layer is formed on the silicon using the chemical vapor deposition (CVD). CVD is the process of depositing a solid material in vapor form to achieve uniform thickness throughout the surface. Then, the trench and via which are part of the BEOL
are made. Using the physical vapor deposition (PVD) method, copper seeds are formed in the trench. Following PVD, the
trenches are filled with copper using the electro-chemical deposition (ECD). The excess copper is removed and very low dielectric roughness is attained by chemical mechanical polishing (CMP). Recessing of copper to a certain level is expected during CMP. As seen in 17 (b), the plasma activated wafers are brought together face-to-face and the dielectrics
are bonded instantaneously. After CMP, annealing is done at 150°C to 300°C, due to which the metal expands to fill the gap between them. The aforementioned steps confirm that Cu-Cu hybrid bonding provides physical and electrical connections
due to the dielectric and metal bonding between the substrates.//