3D NAND manufacturing

3D NAND refers to a type of non-volatile memory (NVM) used globally for data storage (SD cards, SSDs). These devices have a shorter data access time, consume less power, and are more reliable than HDDs due to the absence of moving parts. A flash memory cell is similar to an NMOS transistor: it has a p-well and an n+ source and drain. However, these cells also have a floating gate (FG), a control gate (CG) and an inter-gate dielectric (IGD). The floating gate acts as a charge trap device that prevents electrons from being discharged via the drain. The memory can be erased by discharging the electrons trapped by the IGD to the CG, causing dielectric breakdown. This explains the write and erase limits of these devices.

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All plants producing 3D NAND are presumably located in Asia : South Korea, Singapore, China, Japan. Thanks to their architecture, 3D NAND devices do not require EUV lithography to scale, unlike 2D NAND devices, and have node sizes ranging from 19 to 33 nm (the size of the devices is defined by the half-pitch of the write line pattern). The density of memory cells varies depending on the number of SiO₂ and SiN layers applied in the array area (AA), ranging from 32 to over 400 layers today. One of the biggest challenges in this type of manufacturing is managing the High Aspect Ratio (HAR), the difficulty of which increases mechanically with the number of layers. The critical processes are therefore etching, deposition and cleaning, particularly for the creation of channel holes, isolation trenches, staircase contacts and other HAR patterns.

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Xiao¹⁾ provides the most detailed description of the processes used to manufacture 3D DRAM and NAND devices. Such a detailed public explanation is rare to find and applies only to two types of devices for advanced technology nodes. Nevertheless, it provides a detailed understanding of the various process loops for each mask.

• Wafer clean
• Pad oxidation
• Nitride deposition
• AA mask
• Nitride etch
• PR strip and clean
• Silicon etch
• Wafer clean
• Oxidation
• Oxide deposition
• Oxide CMP
• Strip nitride and pad oxide and wafer clean
• Oxidation of sacrificial oxide
• n-well mask
• n-well and p-channel ion implantation
• PR strip and clean
• Strip sacrificial oxide and wafer clean
• Gate oxidation
• PolySi and silicide deposition
• Poly-dope mask
• Poly-dope ion implantation
• PR strip and clean
• Hard mask deposition
• Gate mask
• Etch hard mask
• PR strip and clean
• Etch silicide/polySi
• Wafer clean
• n-LDD mask
• n-LDD ion implantation
• PR strip and clean
• p-LDD mask
• p-LDD ion implantation
• PR strip and clean
• Spacer dielectric film CVD
• Dielectric etch back
• n-S/D mask
• n-S/D ion implantation
• PR strip and clean
• p-S/D mask
• p-S/D ion implantation
• PR strip and clean
• RTA
• SiN liner deposition
• PMD deposition

• Array area mask
• Etch oxide and barrier nitride
• PR strip and clean
• CVD oxide 1, CVD Nitride 1 and lower SG nitride
• CVD oxide 2, CVD Nitride 2 and lower cell nitride
• CVD oxide 3, Nitride 3 pairs
• Repeating the process until Oxide N/Nitride N
• CVD Oxide N+1 and cap oxide
• First staircase mask
• Etch Oxide N+1/Nitride N, stop on Oxide N
• PR trimming
• Etch Oxide N/Nitride N-1, stop on Oxide N-1
• PR trimming
• Etch Oxide N-1/Nitride N-2, stop on Oxide N-2
• Repeating trimming and O/N pair etch
• PR strip and clean
• Second staircase mask
• Repeating trimming and O/N pair etch
• Third staircase mask
• Repeating trimming and O/N pair etch
• Etch Oxide 1, stop on silicon
• PR strip and wafer clean
• Oxide CVD
• Oxide CMP

• Channel mask
• Etch hard mask
• Etch multi-layers
• Remove hard mask and wafer clean
• SEG Si
• Deposit high-k dielectric
• Deposit charge trap nitride
• Deposit gate oxide
• Etch back channel dielectric layers
• Wafer clean
• Deposit polySi channel
• Deposit silicon oxide filler
• Oxide recess
• Deposit polySi
• PolySi CMP
• Post-CMP clean

• Wafer clean
• Isolation mask
• Etch hard mask
• Etch trenches in ONON multi-layers and stop on silicon
• Remove hard mask
• Remove nitride layers
• Wafer clean
• Oxidation of SEG
• TiN deposition
• W deposition
• Trench W removal
• Trench TiN removal
• Wafer clean
• Oxide deposition
• Oxide etch back
• TiN deposition
• W deposition
• W CMP
• Oxide cap deposition

• Wafer clean
• First contact mask
• Etch hard mask
• Etch shallower staircase contacts
• Strip PR and wafer clean
• Apply the second contact mask and etch staircase contacts
• Strip PR and wafer clean
• Repeating staircase contact litho, etch and clean
• Remove hard mask and wafer clean
• TiN liner deposition
• W deposition
• W CMP
• Wafer clean
• Oxide CVD
• V1 mask
• V1 etch, PR strip, and clean
• Oxide CVD
• M1 mask
• M1 etch, PR strip, and clean
• TiN deposition, W CVD and W CMP
• Oxide CVD
• V2 mask
• V2 etch, PR strip, and clean
• TiN deposition, W CVD, W CMP
• Oxide CVD
• M2 mask
• M2 etch, PR strip, and clean
• TaN deposition, Cu seed deposition, Cu plating, Cu anneal and Cu CMP
• Oxide CVD
• V3 mask
• V3 etch, PR strip, and clean
• TiN deposition, W CVD, W CMP
• PVD TiN, PVD Al-Cu and PVD TiN
• M3 mask
• M3 etch TiN/W/TiN metal stack, PR strip and clean
• Oxide CVD and nitride CVD
• Bond pad mask
• Etch nitride/oxide
• PR strip and clean

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• Cleaning: 40
• Oxidation: 5
• Photolithography: x
• Etching: x
• Doping: 6
• Deposition: 60
• CMP: 6

The total number of process steps depends of the number of layers on the 3D NAND die. Each layer adds 6 process steps (ONON). The repeating steps for each layer are:

• x
• x
• x
• x