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Front-end manufacturing concepts and process flow

Semiconductor manufacturing is among the most complex processes on Earth, if not the most complex. Summarizing the process flow of such an industry in simple terms is difficult given the specific requirements of each type of product produced.

Here, we divide the manufacturing processes into four parts:

Fab production

These processes take place in specialized factories called “fabs.” Most of the time, fabs operate at an average utilization rate of 80%. The manufacturing process involves hundreds of highly sophisticated machines across hundreds of steps—and in some cases, more than 1,000 steps for the most advanced products. According to the Semiconductor Industry Association (SIA), it takes up to 26 weeks to produce a finished chip (front-end processes). The assembly, testing, and packaging stages take an average of 6 weeks (back-end processes).

All the manufacturing processes involved in creating a finished semiconductor wafer, froms start to finish, are referred to as the cycle time. The cycle time is defined my Little's Law, i.e. average inventory (WIP) = throughput time (also called cycle time) x throughput rate. The WIP inventory represents the queue lenght (how many products are being processed at the moment?). The throughput time represents the time in queue (how much time does my product stay in queue?). The throughput rate represents the amount of products processed by unit of time (1 day, 1 week, etc.). For instance, if the throughput time is 10 weeks and the rate 7,000 wafers/week, then the WIP will be 70,000 wafers. Increasing productivity in a fab is determined by these three factors (WIP inventory, throughput rate and time). Note also that the throughput rate depends of the number of steps. Generally speaking, the more advanced the processes are, the higher the throughput rate.

Generally, the most common metric for cycle time in the fab is “days per mask layer”. A “mask layer” includes all of the sequential process recipes (steps) required to manufacture the product up to the next photolithographic step in the process.

The number of layers in a semiconductor chip has a direct impact on its manufacturing cycle time. Chips with higher layer counts require more intricate patterning and deposition processes, which consequently extends the overall manufacturing timeline. For instance, advanced processors designed for high-performance computing or artificial intelligence applications typically have more layers, thus longer cycle times compared to simpler chips like microcontrollers. According to the Electronic Components Industry Association, a 28nm device may have 40 to 50 mask layers ; a 14nm/10nm device has 60 layers ; 7nm 80 to 85 ; a 5nm device could have 100 layers. Generally, the most common metric for cycle time in the fab is “days per mask layer”. So, using DUV lithographic techniques, the cycle times are increasing from roughly 40 days at 28nm, to 60 days at 14nm/10nm, to 80 to 85 days at 7nm. 5nm may extend to 100 days (without extreme ultraviolet (EUV) lithography). Furthermore, cycle time is generally longer when a new process is implemented, but decreases as the process matures.

Another challenge to manage is that as throughput approaches the machines’ maximum effective capacity, cycle time increases, as Martin described in 1999. This is due to the varying idle times between machines—specifically, those capable of handling batches versus those that can only process one or a few wafers at a time.

New advanced nodes (logic and memory) put an additional strain on fab production. According to SEMI : “since 2020, fab cycle times have grown at a compound annual growth rate of 14.8%. This represents a fundamental deceleration in fab throughput, meaning that even with the same number of tools and consistent utilization rates, the volume of wafers that can be processed is now structurally constrained.” They point this growth to “rising process complexity, increased equipment density, and tighter quality control requirements” (equipment spending per wafer area has surged over 150% since 2020). In the case of advanced memory, SEMI notes that “HBM wafers consume over three times more wafer area per bit compared to standard DRAM, creating potentially significant wafer demand.”

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Yield modelling

In addition to the various constraints on productivity, yields are another factor to consider. But 'yield' can refer to many different aspects of the manufacturing process.

According to May & Spanos, the most basic definition, is that of manufacturing yield. This figure 'measures the proportion of successfully fabricated products compared to the number that have started the process'. Wafer yield refers to wafer that get scrapped along the manufacturing process because of equipment malfunctioning, wafer transport problems, etc. Wafer yield can be measured in three ways:

Once a wafer successfully passed this final test, the die can be tested and define the design yield. This yield has two components:

The functional yield test is runned before dicing in order to avoid packaging and shipping of a defective die. The parametric yield is defined after dicing, the dies will then be separated into various performance “bins” depending of parametric variation.

The figure below from May & Spanos summarized the different yield calculation steps.

Manufacturing process flow from the perspective of yield monitoring and control. May & Spanos

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Front-end process flow

Front-end process flow varies widely depending on the target technology nodes and the type of device (logic, memory, etc.). The processes follow a general sequence for each mask: deposition, lithography, etching, doping, resist stripping, and metallization. Each step may be interspersed with intermediate cleaning and inspection steps.

The process flow can be summarized in different ways. From a fab operations perspective, Mönch et al provide a simple view of the looping dynamics on front-end processes.

Operations in a wafer fab. Mönch et al

May and Spanos propose a simplified process flow for a planar CMOS, a simpler flow compared to today's 3D structures.

Operations in a wafer fab. Mönch et al

Going deeper, Plummer et al decompose all the sub-steps that go into a photoresist deposition step for an old manufacturing process. On a more technical view, Franssila shows what happens in an epitaxy reactor, including sub-steps timing and temperature variation.

Typical photoresist process flow for DNQ g-line and i-line positive resists. Plummer et al

Single wafer epitaxy reactor running SiHCl3 process. Franssila

On more recent technology nodes, Jung shows the different steps depending of patterning techniques for logic and DRAM devices. The looping sequences are particulary visible here and shows the complexity depending of selected processes.

Operations in a wafer fab. Mönch et al

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Full process flow for memory devices

Xiao provides the most detailed description of the processes used to manufacture 3D DRAM and NAND devices. Such a detailed public explanation is rare to find and applies only to two types of devices for advanced technology nodes. Nevertheless, it provides a detailed understanding of the various process loops for each mask.

Process flow for 3D devices on DRAM

AA Module

Well formation

BWL module

BLC module

BL and peripheral transistor module

SNC, peripheral contact, and M1 process steps

SN module

V1 and M2 process steps

V2 and M3 process steps

V3-M4 and passivation process steps

Process flow for 3D-NAND Flash

Peripheral CMOS process steps

Multi-layer-deposition and staircase-formation process step

3D NAND channel formation process steps

Process steps for the isolation module of 3D-NAND

Process steps of the contact and interconnect module of 3D-NAND

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