Wafer

This working group focuses on the life cycle inventory of semiconductor manufacturing. We look specifically at wafer and photomask manufacturing, front-end and back-end processes for logic and memory devices .

• Gauthier Roussilhe, Hubblo (Lead)
• Arthur Removille, Resilio
• Eric Fourboul, Hubblo
• Etienne Lees-Perasso, Tide
• Ira Villinger, ETH
• Olivier Soldano, Inria
• Thibault Simon, Resilio
• Matthieu Elizalde, Evea
• William Voghel, CIRAIG

• Modelization strategy
• Front-end manufacturing concepts
• Front-end processes
• Back-end manufacturing concepts
• Back-end processes
• 3D NAND recipe use case
• DRAM recipe use case

This working group focuses only on four different industrial chains to create an open LCI.

Wafer manufacturing refers to the processes involved in fabricating blank wafers made of ultra-pure silicon ready to be used in front-end manufacturing.

Photomask manufacturing refers to the processes involved in fabricating photomasks engraved with a specific circuit design.

Front-end manufacturing refers to the processes used for fabricating a chip’s design onto a raw wafer to yield a die (SIA). It broadly includes: oxidation, photolithography, doping, thin film deposition, metallization, etching, chemical mechanical planarization and metrology.

Back-end manufacturing turns a fabricated wafer into as many as tens of thousands of ready-to-use chips (SIA). It broadly includes: dicing, die attach, bonding, encapsulation and testing.

Silicon wafers are used to manufacture logic (CPU, GPU, ASIC, …) and memory (NAND, RAM, etc.) devices. These devices power most modern electronic and digital equipement requiring computing power, memory storage and connectivity.

Silicon wafers used for integrated circuits (IC) manufacturing are defined as monocrystalline or single-cristal silicon wafers.

These wafers are used to manufacture different types of devices :

• Logic devices: Central Processing Unit (CPU), Graphics Processing Unit (GPU), other Application Specific Integrated Circuit (ASIC), Field Programmable Gate Arrays (FPGA)
• Memory devices: NOR flash, NAND flash (2D and 3D), Random Access Memory (RAM, DRAM, etc.), Synchronous Dynamic RAM (SDRAM, HBM), and other memory devices (FeRAM, etc.)

Depending of devices characteristics, material and processes consumption differ. The biggest parameters that will affect overall consumption and processes involved are :

• node size (expressed in nm or generations Nx),
• number of masks,
• number of layers,
• number of process steps,
• yields,
• throughput.

These parameters affect all types of device mentioned earlier.

Wafer manufacturing has been stable for many years and is a stable market where only wafer size differs (200, 300mm). Single-cristal wafers is a generic component representative of the whole market.

Photomask manufacturing has evolved to answer to industry needs regarding device scaling. A photomask composed of a quartz glass and a chromium layer can be representative of most of the market. However, newer devices at a smaller scale (EUV, etc.) need new materials and technologies.

Some devices can be representative of a specific market or a specific generation but no generalization is possible for logic and memory devices. Model parametrization is necessary to provide a representative assessment of front-end and back-end manufacturing.

Each manufacturing category requires different production lines and steps. All the sub-parts regarding manufacturing will be defined in the dedicated pages below.

Other sub-parts relate to specific flows necessary for semiconductor manufacturing such as Ultra-Pure Water (UPW). However, for now we don't intend to address this kind of sub-parts.

We include manufacturing stages for single-cristal wafers, photomasks, front-end and back-end processes for CPU, NAND and RAM devices.

For now, several devices are excluded : GPU, FPGA, SDRAM (HBM).

We exclude research and development, chip design (except for photomasks manufacturing) and later stages after chips exit the final production line.

We also focus on silicon-based chips, excluding de facto germanium, gallium, indium phosphide-based and other substrates that are used for different applications (power electronics, lasers, etc.

The functional unit is yet to be determined.

Historically, the environmental footprint of integrated circuit manufacturing has been defined by the following UF: the production of cm²/die. This functional unit is calculated by determining the manufacturing footprint of m² of wafer and then accounting for various losses associated with the kerf, defect density, die format and other yield parameters.

Other proxies may be used to complement a chip’s manufacturing footprint: the number of manufacturing steps¹⁾; the average environmental footprint of each type of process multiplied by the number of steps per process²⁾; the average footprint based on a fab’s throughput³⁾; or a bottom-up approach for analysts with access to primary data from a fab.

Recent works also point out that allocation of impacts could differ depending of binning, i.e. differentiation of a lot according to performance, and then implying a price-based and performance-based allocation⁴⁾.

The cm²/die ratio depends entirely on knowing the exact die area, which is not automatically provided by manufacturers. This area is not directly accessible or visible as it is covered by the packaging. Consequently, an inaccurate estimate of the die area can cause significant variations in the footprint of a chip and the equipment that houses it. Proske et al provide a database of die-to-package ratios based on direct measurement or radiographic imaging of 189 chips⁵⁾ to circumvent this issue.

The reference flow is yet to be determined.

The reference flow is historically a m² of manufactured wafer for wafer and front-end manufacturing. Photomask and back-end manufacturing have yet to be defined.

Regarding front-end manufacturing, Pirson et al provide a comprehensive review of historical and actual trends regarding environmental impacts of IC production per technology nodes and based on scientific literature and LCA databases⁶⁾.

Furthermore, several datasets and models already exist from LCA databases such as:

• Negaoctet's dataset
• Resilio's database
• ecoinvent

Several parametric models are also available from industry specialists:

• imec.netzero app
• TechInsight's Semiconductor Manufacturing Carbon Module

A silicon wafer is made from single-crystal silicon, which is derived from high-purity sand.

• Front-end manufacturing flow
• Front-end processes
• Back-end manufacturing flow
• Back-end processes
• 3D NAND use case
• DRAM use case

The process involves purifying the sand, melting it, and re-crystallizing it into a large, pure silicon ingot (Czochralski process). This ingot is then sliced into thin discs, which are polished to a mirror-like finish to form the wafer.

Once the disks are obtained, the main steps are:

• Wafer Production: The process begins with creating wafers from pure crystalline silicon. Silicon ingots are sawed into wafers using diamond-coated wire. These wafers, ranging in diameters from 100 mm to 300 mm, are then polished to achieve an even and clean surface, essential for preventing defects and ensuring the integrity of the semiconductor devices.
• Deposition: Thin films of materials, typically oxides, are deposited on the wafer. This process can be physical or chemical, creating a mask layer necessary for subsequent patterning steps.
• Photolithography: Photolithography is a critical process in defining the intricate patterns of integrated circuits (ICs). It involves applying a photoresist layer to the wafer, which is then exposed to a light source through a photomask to project the desired circuit pattern onto the photoresist. The resolution of this process, determined by the wavelength of the light source, dictates the size of the semiconductor nodes. There are various types of photolithography used in semiconductor manufacturing:
  • DUV (Deep Ultra-Violet) Lithography: Uses KrF (248 nm) for nodes ≥150 nm and ArF (193 nm) in dry (≥65 nm) and immersion forms (≥7 nm).
  • EUV (Extreme Ultra-Violet) Lithography: Employs a 13.5 nm light source, achieving the smallest nodes, such as 5 nm.

The resolution of each photolithography technique directly impacts the achievable node size, with EUV technology leading the way in current semiconductor advancements.

• Etching: This step removes parts of the photoresist and oxide layer exposed by the laser, creating the desired patterns on the wafer. Etching can be performed using either dry (plasma-phase) or wet (liquid-phase) techniques.
• Doping: Introducing small amounts of charged particles to modify the electrical properties of the wafer surface. Doping is achieved through ion implantation or diffusion, creating regions of p-type or n-type semiconductor material.
• Stripping: Removing unwanted photoresist layers from the wafer. This can be done using organic, inorganic, or dry stripping methods.
• Back-End-of-Line (BEOL) Process: After front-end-of-line (FEOL) processing, the BEOL process involves depositing metal wiring to interconnect the transistors on the wafer. This process includes additional layers of photoresist application, UV exposure, and etching, adding 5 to 12 more layers to the wafer.
• Repetition and Layering: The entire process is repeated 40 to 100 times to build multiple layers necessary for complex integrated circuits.
• Dicing and Packaging: Once the wafer processing cycle is complete, the wafer is diced into individual chips. These chips are tested for functionality and then encapsulated in protective packages to prevent physical damage and corrosion.
• Final Testing: Ensures the integrity and functionality of the chips post-packaging, verifying that they meet the required specifications before being deployed in electronic devices.

For logic wafers: Intel, AMD, Qualcomm. They rely on foundires like TSMC and GlobalFoundries. For memory wafers:

• NAND: Samsung, Kioxia, Western Digital
• DRAM: Samsung, SK Hynix, Micron Technology ⁷⁾

The semiconductor industry is comprised of three main types of companies, each playing a distinct role:

• IDMs (Integrated Device Manufacturers): Perform all stages from design to manufacturing and sales in-house. Examples include Intel, Texas Instruments, Samsung Electronics, and Micron Technology.
• Fabless Companies: Design and sell chips but outsource manufacturing to foundries. Notable fabless companies are Nvidia, Qualcomm, AMD, Apple, Broadcom, MediaTek, and Marvell Technology Group.
• Foundries: Manufacture wafers based on client designs. Leading foundries are TSMC, UMC, GlobalFoundries, SMIC, and Samsung Foundry.

Additionally, it is increasingly common for IDMs to outsource part of their production to foundries. Some IDMs, like IBM and Samsung, also offer foundry services to fabless companies.

The Asia Pacific region is the largest semiconductor industry region, with China as the leading single-country market. Despite a 15% decline since 2021, China's market remains critical. The Americas and Europe show resilience, with Europe's market growing by 4% in 2023. Japan experienced a slight decline, reflecting the competitive nature of the market. These regional dynamics underscore the semiconductor industry's global interconnectedness and sensitivity to geopolitical and economic factors. ⁸⁾

The global semiconductor manufacturing industry is highly concentrated in East Asia, the United States, and the European Union with these regions housing over 90% of all facilities. East Asia, with 292 sites, represents around 66% of the total, dominating global chip production. Taiwan alone produces 60% of the world's semiconductors and 90% of the most advanced ones, especially logic chips. Additionally, Korean companies hold a commanding 60% share of the memory chip market. This map visualizes the geographic distribution and processing capabilities of semiconductor manufacturing facilities.

Cutting-edge wafer fabrication, particularly at nodes of 7nm or less, is predominantly found in South Korea and Taiwan. Europe, on the other hand, lacks these advanced facilities and as a consequence lags in adopting more mature technology nodes. A tiny share of wafer capacity for nodes between 10nm to 20nm exists in Europe, mainly due to Intel’s fabs in Ireland and Israel, which are currently not available for contract manufacturing. Furthermore, European fabs like those from STMicroelectronics and GlobalFoundriesoperate nodes from 22nm to 40nm, but the majority of Europe’s capacity (almost 50%) consists of older nodes of 180nm or larger, used extensively for automotive and industrial applications. ⁹⁾

TBC

Not in the scope

Not in the scope

The main impacts are:

• The electricity consumption: Some manufacturing steps are very energy-intensive: deposition, lithography, and etching. The value depends on the technology node (lithography) because the equipment used and the number of steps in the process are not the same.
• The electricity impacts are also linked to the electric mix of the country or geographical region(s) where it is located.
• Process gases: Various gases are used during the process, mostly for chemical vapor deposition and dry etch processes. However, the gases may not be entirely consumed, or gaseous by-products may be generated. Gas abatement techniques are applied, involving cracking the gases into less harmful compounds. The various gas emissions that are considered are the following: SF6, NF3, N2O, CO2, CHF3, CF4, C4F8, C2F6. Gas abatement is generally used in the process to reduce the amount of emitted gases.
• Water consumption: During wafer processing, a certain amount of water is required. Approximately 76% of this water is used to generate ultra-pure water (UPW), mainly for chemical mechanical planarization and wet cleaning steps. A production yield of 62.5% is assumed. The remaining water is used as is.

• Device type (logic, DRAM or NAND)
• Diameter of the wafer (mm)
• Surface of the final die (mm2)
• Lithography (nm)
• Yield of the process
• The manufacturing location

To help you understand the complexity of semiconductor manufacturing processes, we have created a glossary to bring together key terms and acronyms.

• Glossary

• The purity of the silicon crystal is not properly taken into account in the existing LCAs

TBC

• Confront Negaoctet's datasets and imec results in order to understand what are the reasons for the differences
• Estimate the environmental impact of the wafer packaging wafer packaging

• Glossary