Modelization strategy

The aim of this working group is to enable the quantification of the environmental impacts associated with the manufacture of various types of integrated circuits.

These manufacturing processes are the most complex in the world, and each manufacturer has its own way of organising production and utilising processes depending on the target devices (logic, RAM, NAND, X nm, X layers, etc.), which constitute their trade secrets. Access to consistent and representative production data is the biggest challenge facing this project.

We must therefore find a way to improve existing quantification models, which are generally based on the impact per cm² of die, modified by a number of parameters (layers, yield, location, node size, etc.). We must also produce an initial open model that will allow for contributions and continuous improvement.

The objectives of the model are therefore :

• to improve existing models
• to make it open
• to be robust enough for manufacturers and other players in the semiconductor sector to be able to use and improve it
• to be representative enough of different production setups and technology nodes
• to respect confidentiality and trade secrets of manufacturers and companies along the value chain
• to provide a solid foundation for ongoing contribution and improvement over time
• to be customisable for stakeholders who have their own operational data

Our model must meet these objectives, even if they are potentially contradictory under adverse conditions. Above you can see how we have designed our quantification model to take all these objectives into account.

In an ideal world, we would like to have the recipe for every type of integrated circuit produced. A recipe contains detailed instructions to process the wafer (temperature, pressure, chemicals and gases used, dilution of chemicals, amount of time, etc.). A recipe is a trade secret so only recipes for decommisionned/old products might be publicly available today.

A recipe combined with measurements from wafer fab equipments (WFE) deployed on the clean room floor would allow to have a clearer picture of all the inputs and outputs at stake while manufacturing integrated circuits, hence their environmental footprint. Yet again, only foundries and labs have production clean rooms (with more or less measurement apparatus). So, primary data is mostly only available to manufacturers and specialized labs.

A traveler provides the sequential list of all the steps a wafer must go through and the areas of the cleanroom to which the wafer must be transported for each step. A traveler provides far less information about the processes and their calibration, but it does indicate the total number of steps and the types of processes involved.

Our approach is based on three key factors:

• Average total number of steps for a finished device
• Average distribution of steps per process type for a finished device
• Average inputs and outputs per process type for one step

Our aim is to define archetypes, defining these three factors, for each type of device (logic, DRAM, NAND) and their key characteristics (node size for logic and DRAM, number of layers for NAND).

These factors are, of course, supplemented by traditional parameters used in this type of assessment, such as:

• die size
• die yield
• fab location
• fab capacity
• fab utilization
• fab abatment
• fab overhead
• etc.

This approach provides a more precise quantification than the classic approach based on cm² per die. However, imec.netzero might already follow the same approach [To be discussed]

Our approach, based on averages, aims to respect the trade secrets of manufacturers and laboratories. We don't need the precise total number of steps and the process type distribution, we just need to agree on representative averages (with min, max if possible). Working with average inputs/outputs per process type (CVD, dry etch, photolitho, etc.) allows to share agregate data that doesn't show actual recipes.

[To be completed]

[To be completed]