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Back-End-of-Line (BEOL) Sequence

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Back-End

1. Wafer thinning

Processes

1.1. First optical inspection

  • Electricity

Expliquer le process First optical inspection : 5-10 lignes

1.2. Taping

  • Electricity
  • Tape (PVC)
  • Process Water (DI)
  • Ultrapure Water
  • Air
  • Exhaust

1.3. Grinding

  • Electricity
  • Tape
  • Process Water
  • Ultrapure Water
  • Air
  • Exhaust

Manufacturers

Equipment

Sources

  • IMEC

2. Wafer bumping

Wafer bumping creates metal/solder bumps on pads (electroplated) and wafer-level packaging. Using polyimide to create dielectric/passivation structure and the metals stack to form the bump foundation and final solderable surface. To simplify, there are three main steps in this process: surface preparation and polyimide dielectric; pattern opening and plating areas with lithography; and solder deposition and reflow.

Processes

2.1. Plasma cleaning

Oxygen or nitrogen plasma is used for organic removal, which changes how polyimide and copper surface interact. Optimizing process parameters can increase the interface shear strength of PI-on-PI and PI-on-Cu structures, but must avoid damaging aluminum pads, alter Cu surface chemistry, or fragile passivation. ^^

Input

  • Wafer with residual organics/oxide
  • Electricity
  • Process gases
  • Vacuum/pumping power

Output

  • Cleaned/activated wafer surface
  • Exhaust gases
  • Heat

2.2. Polyimide Spin coating

Spin coating works by dispensing liquid polyimide precursor onto the wafer surface (RDL) followed by centrifugal force spreads the film. This dielectric layer also helps to relieve stress between silicon and the underbump metallization (UBM).

A good polyimide coating needs to be uniform across the wafer, because thickness variation can cause problems via depth, stress, warpage, and bump height.^^

Input

  • Polyimide precursor
  • Solvent
  • Electricity

Output

  • Uniform polyimide film on wafer
  • Spent solvent
  • Wastewater

2.3. Polyimide Photolithography

The goal is to expose parts of the seed layer or pad underneath for bump formation while leaving the rest of the wafer insulated and providing mechanical support. Proper alignment of the openings is critical because they must match the pad or redistribution features with good overlay, especially for fine-pitch wafers.^^

Input

  • Photoresist or photosensitive polyimide layer
  • Mask
  • Developer chemistry
  • DI water
  • Electricity

Output

  • Patterned/defined polyimide openings
  • Developer waste
  • Rinse wastewater
  • Spent mask

2.4. Polyimide Development

Development removes exposed or unexposed, depending on chemistry that is being used. The development process makes the openings that are needed for the metal to make contact on. The geometry of these openings can have a significant impact because it affects how the metal gets into the openings and the final shape of the bumps.

Input

  • Developer chemistry
  • DI water
  • Agitation

Output

  • Opened via/feature pattern
  • Wastewater
  • Chemical waste

2.5. Polyimide Curing

Curing is a process that changes the spin-coated precursor into a stable film by removing the solvents and finishing the imidization or crosslinking process. Curing conditions that are utilized have a direct impact on a number of important properties such as film stress, dielectric constant, mechanical hardness, moisture uptake and wafer bow. If the cure is incomplete or not uniform, residual solvent may be left in the film, leading to blistering or delamination of the film during later use. The cure is performed as multiple stages to minimize the occurrence of cracking: first there is a soft bake or intermediate drying stage followed by higher temperature curing under controlled ramp rates (up and down).

Input

  • Heat
  • Nitrogen or inert atmosphere
  • Electricity

Output

  • Cured polyimide dielectric
  • Outgassed volatiles

2.6. Seed layer deposition (PVD)

The seed layer is deposited by physical vapor deposition to create a thin conductive film over the wafer that allows for electroplating and serves as the first part of the UBM stack. In bumping, this layer is frequently Cu-based (often with barrier like Ti/Ni) or may consist of a multilayer stack such as Ti/Cu or equivalent materials. The barrier component adheres to the substrate wafer or dielectric while the conductive element ensures uniform current distribution during plating operations. If there are any discontinuities in the seed layer, then one might find missing bumps after plating due to non-uniformity; hence thickness and coverage over topography become critical parameters to control.

Input

  • Wafer
  • Target metals such as Ti/Cu or similar seed stack
  • Electricity

Output

  • Thin conductive seed film
  • Heat

2.7. Spin coating

This second spin coating step is associated with coating the photoresist rather than applying the polyimide layer. A thick resist coating is necessary since plating masks require substantial thickness to create well-defined electroplating cavities characterized by a high aspect ratio and clean sidewalls. In wafer bumping, resist thickness, edge bead removal, and uniformity are critical as it determines the eventual bump diameter and whether plating will result in copper mushrooms or copper being undercuts.

Input

  • Photoresist
  • Solvent
  • Electricity

Output

  • Uniform resist film
  • Solvent vapor

2.8. Photolithography

The photolithography process uses a mask to expose resist that defines the areas where copper or solder will be plated. The exposed areas on the photoresist film correlate with the location of the bumps or copper pillars, and it needs to be controlled because the plated feature size is directly related to the lithographic aperture.

Input

  • Photoresist-coated wafer
  • Mask

Output

  • Exposed resist pattern

2.9. Development & soft baking

Once photoresist has been exposed to the photoresist analyzing light (UV), development opens vertical-walled cavities that define bump diameter and height. While soft bake is used to drive out the solvent and stabilize the resist before plating.

Input

  • Developer
  • DI water

Output

  • Plating mold with openings
  • Developer waste

2.10. Plasma cleaning

The second plasma cleaning is used to remove microscopic residue after the resist development step and to activate exposed surfaces. It also helps lower the amount of trapped contamination causing issues with solder wetting and seed etch uniformity in advanced packaging.

Input

  • Plasma gases
  • Electricity
  • Vacuum power

Output

  • Activated/cleaned plating surface
  • Exhaust gases

2.11. Copper plating

Input

  • Plating bath
  • Copper sulfate or equivalent source
  • Acid
  • Electricity

Output

  • Electroplated copper features or pillars
  • Wastewater
  • Heat

2.12. Resin stripping

Input

  • Strip chemistry
  • Heat
  • DI water
  • Electricity

Output

  • Stripped wafer with plated structures exposed
  • Chemical waste
  • VOCs

2.13. Wet etching

Input

  • Etchant for seed/UBM removal
  • DI water
  • Electricity

Output

  • Isolated plated bumps/pillars
  • Etched seed/metal waste in solution
  • Spent etchant

2.14. Bump reflow

Input

  • Wafer with plated bumps or solder balls
  • Inert gas (N2) or forming gas
  • Electricity

Output

  • Rounded reflowed bumps
  • Heat

Misc

See Front-end processes

Manufacturers

Equipment

Sources

  • OSAT
  • IMEC
  • Liu, Wei-Wei, et al. “Plasma Treatment for Robust Interface Adhesion of Wafer Level Packaging.” 2021 16th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT). IEEE, 2021.
  • Dong, Zihao, et al. “Microfabrication of functional polyimide films and microstructures for flexible MEMS applications.” Microsystems & Nanoengineering 9.1 (2023): 31.
  • Diaham, Sombel. “Polyimide in Electronics: Applications and Processability.” Polyimide for Electronic and Electrical Engineering Applications (2021): 3.
  • Ma, Mike, et al. “The development and the integration of the 5 µm to 1 µm half pitches wafer level cu redistribution layers.” 2016 IEEE 66th Electronic Components and Technology Conference (ECTC). IEEE, 2016.
  • Foutz, Eugene L. “Process for curing polyimide.” U.S. Patent No. 4,643,910. 17 Feb. 1987.
  • Datta, Madhav. “Manufacturing processes for fabrication of flip-chip micro-bumps used in microelectronic packaging: An overview.” Journal of Micromanufacturing 3.1 (2020): 69-83.
  • da Silveira, Elvino, and S. Gardner. “Advances in wafer level and chip scale packaging.” IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium (IEEE Cat. No. 04CH37585). IEEE, 2004.

3. Dicing

Processes

3.1. Wafer mounting

Input

  • Wafer with back metallization
  • Dicing tape (PVC)
  • Electricity

Output

  • Mounted wafer on tape
  • Heat

3.2. Laser grooving

When choosing a process, it must balance the shape of the groove (for example U-shape) against narrow street size. Also, laser wavelength, beam size, multi-pass method, power; speed, frequency, pitting, and residues.

Using ultrashort-pulse (USP) UV grooving can make the edges of the material better reduce the amount of burr, and supports the die be stronger when plasma dicing is combined.^^

  • Electricity
  • N2
  • Air
  • Ultrapure Water
  • Waste Water

3.3. Blade singulation

- Electricity - Blade - Process Water - Air - Exhaust

3.4. UV Irradiation

- Electricity

3.5. 2nd Automated Optical Inspection

- Electricity

Manufacturers

Equipment

Sources

  • IMEC

4. Die attach

Once the die are diced, only the selected dies from the wafer map are mounted on the lead frames or substrates using solder, epoxy, or DAF adhesive. The mounting process involves curing/reflowing, wire bonding/flip chip interconnect, encapsulation, and testing. The machine problems and inefficiencies in the pick-and-place movements influence efficiency; genetic algorithms and statistical fault modeling can be used to improve the robot movement and critical factors for shorter transfers.

Processes

4.1. Unit Substrate Bar-Coding

The back-end manufacturing plants implement mixed consignment production. Strip-level and substrate-level bar-coding is used for the traceability of device type, lot number, and processing, but details about the bar-coding schemes are not provided in the abstracts.

- Electricity - Exhaust

4.2. Fluxing & Flip-Chip Attach

The flip-chip attachment of die uses either solder bumps or copper pillars with solder micro-bumps and flux to eliminate oxides and allow for wetting to occur between the die and substrate.

- Electricity - Flux - N2

4.3. Reflow

Reflow processes should completely wet the solder, provide coplanarity and height control of bumps, and prevent void formation or non-wet opens. The use of 3D laser measuring equipment to measure coplanarity and bump height is essential for process control and quality assurance in flip chip applications.

- Electricity - N2 - Exhaust

4.4. Cleaning

When traditional fluxes are used, the subsequent cleaning step in an aqueous medium should effectively clean residues, considering that the clearance is extremely small and that the die thickness is limited.

- Electricity - Ultrapure Water - Waster Water

4.5. Automated Optical Inspection

  • Electricity

Manufacturers

Equipment

Sources

  • IMEC
  • Park, You-Jin, and Sun Hur. “Improvement of productivity through the reduction of unexpected equipment faults in die attach equipment.” Processes 8.4 (2020): 394.
  • Lim, SzePei, et al. “Flux challenges in flip-chip die-attach.” 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC). IEEE, 2015.

5. Underfilling

Processes

5.1. Capillary Underfill Pre-Bake

- Electricity - Exhaust

5.2. Plasma Clean

- Electricity - O2 - Exhaust

5.3. Adhesive Application

- Electricity - N2 - Adhesive (underfill) - Exhaust

5.4. Curing

  • Electricity
  • N2
  • Exhaust

5.5. 3rd Aumtomated Optical Inspection

  • Electricity

Manufacturers

Equipment

Sources

  • IMEC
  • Plachý, Zbyněk, et al. “Underfill: a review of reliability improvement methods in electronics production.” Polymers 17.16 (2025): 2206.
  • Tong, Q., et al. “Recent advances on a wafer-level flip chip packaging process.” 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No. 00CH37070). IEEE, 2000.

6. Lid Attach

Processes

6.1. Thermal Interface Application

  • Electricity
  • Thermal Interface Material

6.2. Lid Attach

  • Electricity
  • Air
  • Exhaust

6.3. Lid Attach Cure

  • Electricity
  • N2
  • Exhaust

Manufacturers

Equipments

Sources

  • IMEC

7. Molding

Processes

7.1. Plasma Clean

  • Electricity
  • Exhaust

7.2. Transfer Mold

- Electricity - Exhaust

7.3. Post Mold Cure

  • Electricity
  • N2
  • Exhaust

Manufacturers

Equipment

Sources

  • IMEC

8. Marking

Processes

8.1. Laser Marking Strip

  • Electricity

Manufacturers

Equipment

Sources

  • IMEC

9. Ball Attach

Processes

9.1. Pre-Clean & Placement

  • Electricity
  • N2
  • Exhaust

9.2. Fluxing

  • Electricity
  • N2
  • Exhaust

9.3. Ball Attach

  • Electricity
  • N2
  • Exhaust

9.4. Solder Ball Reflow

  • Electricity
  • N2
  • Exhaust

9.5. Flux Cleaning

  • Electricity
  • Ultrapure Water
  • Waste Water

Manufacturers

Equipment

Sources

  • IMEC

10. Singulation

Processes

10.1. Dimension check

  • Electricity

10.2. Automated Optical Inspection

  • Electricity

Manufacturers

Equipment

Sources

  • IMEC

11. Testing

Processes

  • Electricity

Others

  • The electricity consumed per CPU testing in 2x the CPU thermal power dissipation

Manufacturers

Equipment

Sources

  • IMEC
  • Advantest

12. Wire Bonding

Processes

  • Gold

Manufacturers

Equipment

Sources

Discussion

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