After the dies are tested for functionality and binned, they are packaged. Plastic or ceramic packaging involves mounting the die, connecting the die/bond pads to the pins on the package, and sealing the die. Tiny bondwires are used to connect the pads to the pins. In the 'old days' (1970s), wires were attached by hand, but now specialized machines perform the task. Traditionally, these wires have been composed of gold, leading to a lead frame (pronounced “leed frame”) of solder-plated copper; lead is poisonous, so lead-free “lead frames” are now mandated by RoHS. Traditionally the bond pads are located on the edges of the die, however, Flip-chip packaging can be used to place bond pads across the entire surface of the die.

Chip scale package (CSP) is another packaging technology. A plastic dual in-line package, like most packages, is many times larger than the actual die hidden inside, whereas CSP chips are nearly the size of the die; a CSP can be constructed for each die before the wafer is diced.

The packaged chips are retested to ensure that they were not damaged during packaging and that the die-to-pin interconnect operation was performed correctly. A laser then etches the chip's name and numbers on the package. The steps involving testing and packaging of dies, followed by final testing of finished, packaged chips, are called the back end, post-fab, ATMP (Assembly, Test, Marking, and Packaging) or ATP (Assembly, Test and Packaging) of semiconductor manufacturing, and may be carried out by OSAT (OutSourced Assembly and Test) companies which are separate from semiconductor foundries. A foundry is a company or fab performing manufacturing processes such as photolithography and etching that are part of the front end of semiconductor manufacturing. ¹⁾

The semiconductor supply chain is highly regionalized. Front-end manufacturing (wafer fabrication) is dominated by a handful of players, primarily in East Asia. Back-end processes, particularly packaging and testing, are concentrated in Taiwan, South Korea, Malaysia, and mainland China, with limited capacity in the United States ²⁾. This geographic concentration introduces both operational efficiency and systemic risk, especially as geopolitical tensions increase.

Back-end manufacturing is essential and nearly all integrated circuits (ICs) must be encapsulated to protect the die, enable thermal management, and provide electrical connectivity. Without encapsulation, no chip can be integrated into a device.

The industry operates under a tripartite model:

• Fabless companies (e.g., Apple, NVIDIA, Qualcomm) design chips but outsource manufacturing.
• Foundries (e.g., TSMC, Samsung Foundry, Intel Foundry) manufacture wafers based on customer designs.
• OSATs (Outsourced Semiconductor Assembly and Test) (e.g., ASE, Amkor, and JCET) handle packaging, encapsulation, testing, and final assembly.

This division of labor enables specialization but also fragments environmental accountability across borders and corporate entities.

A complete CPU assembly consists of ³⁾:

• Substrate (base layer),
• Die (silicon core),
• Heat spreader (top metallic layer), which interfaces with cooling solutions to manage thermal output

The interconnection method between the die and substrate can also be of two types ⁴⁾:

• Flip Chip: Modern method using solder bumps and underfill polymer on chip pads for direct interconnection between the die and the substrate ⁵⁾,
• Wire Bonding: Traditional method using fine wires (Aluminum, Copper, Silver, Gold) to connect die to substrate ⁶⁾.

Each method will have a specific process flow with different steps during the manufacturing in the fabrication plant.

CPU sockets enable installation, replacement, or maintenance on motherboards, primarily used in desktops and servers. The socket is screwed directly into the motherboard. Since the socket and the substrate have to fit into each other, the choice of socket influence the choice of substrate. The two dominant types are ⁷⁾:

• Land Grid Array (LGA): uses flat contact pads (“lands”) on the package underside, aligned with matching PCB pads, and can be mounted via socket or surface-mount soldering, it has no solder balls, relying instead on direct solder or spring contacts for connection ⁸⁾,
• Pin Grid Array (PGA): is a square or rectangular integrated circuit package with pins arranged in a uniform grid on its underside for connection to a PCB, it relies on physical pins rather than solder balls or flat contacts ⁹⁾.

For the CPUs that will not be removed, the connection to the motherboard is done through the Ball Grid Array (BGA) method, it is typically used for laptops or smartphones where direct access to the CPUs is not useful. The BGA evolved from the PGA, replacing its grid of pins with solder balls on the package’s underside, which connect to matching PCB pads when heated and melted. During reflow, surface tension aligns the package precisely as the solder solidifies, creating reliable electrical and mechanical bonds ¹⁰⁾.

Back end manufacturing can be categorize between the following groups:

• LGA (Land Grid Array): used by Intel for desktop CPUs. Pins are on the motherboard; CPU has flat contacts. Installation involves alignment and pressure.
• PGA (Pin Grid Array): used by AMD for desktop CPUs. Pins are on the CPU, motherboard has receptacles. Installation involves insertion.
• BGA (Ball Grid Array): used in mobile devices (laptops, tablets). CPU is soldered directly to the PCB via spherical solder joints. Non-detachable.
• FC-BGA (Flip-Chip BGA): more space-efficient; chip is flipped and soldered directly to PCB ¹¹⁾.
• WLP(Wafer-Level Packaging): encapsulation occurs before wafer dicing, it is typically used for very small equipment such as headphones ¹²⁾.

Other types of processes exists such as QFN, DFN ¹³⁾ which are not covered in the first project of naKnow.

• First Optical Inspection
• Taping
• Grinding
• Visual Inspection

• Plasma cleaning
• Spin coating
• Photo-lithography
• Development & soft baking
• Plasma cleaning
• Copper plating
• Resin stripping
• Wet etching
• Bump reflow

• Wafer mounting
• Laser grooving
• Blade singulation
• UV irradiation
• Second optical inspection

• Unit substrate bar-coding
• Fluxing & flip chip attach
• Reflow
• Cleaning
• Visual Inspection

See encapsulation page

• Laser marking strip

Ball attached to substrate

• Pre-clean & placement
• Fluxing
• Ball attach
• Solder ball reflow
• Flux clean

• Dimension check
• Check inspection

• First optical inspection
• Taping
• Grinding
• Visual inspection

• Wafer mounting
• Laser grooving
• Blade singulation
• UV irradiation
• Second optical inspection

• Die attach to carrier
• Wire bonding

See encapsulation page

• Laser marking strip

Ball attach to substrate

• Pre-clean & Placement
• Fluxing
• Ball attach
• Solder ball reflow
• Flux clean

• Dimension check
• Visual inspection