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Overview of semiconductor packaging

State of the art information for semiconductor packaging

Introduction

Definition

A semiconductor package is a metal, plastic, glass, or ceramic casing containing one or more discrete semiconductor devices or integrated circuits. Individual components are fabricated on semiconductor wafers (commonly silicon) before being diced into die, tested, and packaged. The package provides a means for connecting it to the external environment, such as printed circuit board, via leads such as lands, balls, or pins; and protection against threats such as mechanical impact, chemical contamination, and light exposure. Additionally, it helps dissipate heat produced by the device, with or without the aid of a heat spreader. (Wikipédia:https://en.wikipedia.org/wiki/Semiconductor_package)

What is it used for?

Packaging is necessary for all electronic components some examples are the RAMs, CPUs, GPUs, SSDs, etc…

Are they different types and technologies?

Yes there are many different types of semiconductor packaging depending on the machine where the component will be used.

Here we focus on the packaging used for central processing units (CPU).

Several packaging technologies exist we can distinguish two levels of packaging: * Wafer level chip scale packaging where the packaging processes of the CPU are realised directly on the wafer, it allows for much smaller packages and is typically used for phones or wireless earphones where the space is limited. * Panel level packaging where the packaging processes happen between the carrier which is a PCB substrate and the die once it has been singulated from the wafer. Here we can categorise 2 types of packaging depending on the method used to connect the die pins to the carrier pins :

  • Wire bonding technology : the die is glued to the carrier and wires are used to connect the carrier pins to the die pins, gold is the material typically used for the wire bonding. Some modling material will be then poured on the die and the wire to protect the wires and the die actives circuits.
  • Flip-chip technology : metallic solder bump are deposited on the die active circuit which is then flipped and put on the carrier where the bumps will serve as a connexion, an underfill material will be then poured between the die and the carrier around the bumps to disminish the mecanical stress and improve the strength of the CPU.

The CPU can be connected to the rest of the motherboard using 2 types of connexions : * Socket connexion : it is the preferred method for servers and desktops applications since it allows to remove to remplace, upgrade or repare the CPU. The socket is screwed to the motherboard and the CPU is manually inserted inside. The most common method of connexion is used by Intel and is called land grid array (LGA) where the CPU carrier bottom connexion will be an array of gold pads and the pins will be on the socket. The CPU carrier bottom connexions will be a pin grid array (PGA), which is typically used by AMD, each pin will found its female counter part on the socket. * Ball grid array connexion : this method is more space and thermically efficient but does not allow the removal of the CPU, it is typically used in laptop and some phones. Metallic solder balls are placed on the CPU and will be directly solder to the motherboard.

Manufacturing

What is it made of?

TBC

How is it manufactured?

TBC

Who are the main manufacturers?

The main manufacturer of the CPU carrier is the japanese company Ibiden. The main CPU packaging companies are the Outsources Semiconductor Assembly and Testing (OSATs) companies which are JCET, Amkor and ASE.

Where are they located?

These companies are all located in South East Asia.

Environmental footprint

What are the main environmental impacts associated to the materials?

TBC

What are the main environmental impacts associated to the manufacturing processes?

TBC

What are the potential parameters affecting environmental impact?

TBC

Already existing data? (dataset, parametric model, paper, etc.)

Negaoctet's datasets, imec tool.

Next steps

What do we know we don't know?

TBC

What are the identified challenges?

TBC

What paths/ideas should be explored?

TBC

categorie/page.1764952224.txt.gz · Dernière modification : de arthur