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fab-process-flow.md [2026/03/24 15:03] – gauthier.roussilhe.extfab-process-flow.md [2026/03/27 09:58] (current) – [Full process flow for memory devices] gauthier.roussilhe.ext
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-# Semiconductor manufacturing processes+# Front-end manufacturing concepts and process flow
  
 Semiconductor manufacturing is among the most complex processes on Earth, if not the most complex. Summarizing the process flow of such an industry in simple terms is difficult given the specific requirements of each type of product produced.  Semiconductor manufacturing is among the most complex processes on Earth, if not the most complex. Summarizing the process flow of such an industry in simple terms is difficult given the specific requirements of each type of product produced. 
  
 Here, we divide the manufacturing processes into four parts: Here, we divide the manufacturing processes into four parts:
-  * Wafer fabrication+  * wafer fabrication
   * photomask fabrication   * photomask fabrication
   * front-end processes   * front-end processes
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 ### Sources ### Sources
  
-- Mönch, L., Fowler, J. W., & Mason, S. J. (2012). Production planning and control for semiconductor wafer fabrication facilities: modeling, analysis, and systems. Springer Science & Business Media. +  * Mönch, L., Fowler, J. W., & Mason, S. J. (2012). Production planning and control for semiconductor wafer fabrication facilities: modeling, analysis, and systems. Springer Science & Business Media. 
-- Micron. (2026). An application of Little's Law in Micron’s supply chain. +  * Micron. (2026). An application of Little's Law in Micron’s supply chain. 
-- Martin, D. P. (1999, September). Total operational efficiency (TOE): the determination of two capacity and cycle time components and their relationship to productivity improvements in a semiconductor manufacturing line. In 10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No. 99CH36295) (pp. 37-41). IEEE. +  * Martin, D. P. (1999, September). Total operational efficiency (TOE): the determination of two capacity and cycle time components and their relationship to productivity improvements in a semiconductor manufacturing line. In 10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No. 99CH36295) (pp. 37-41). IEEE. 
-- Ibrahim, K., Chik, M., & Hashim, U. (2016). Semiconductor Fabrication Strategy for Cycle Time and Capacity Optimization: Past and Present. In Proceedings of the 2016 International Conference on Industrial Engineering and Operations Management (No. 1, pp. 2798-2807). +  * Ibrahim, K., Chik, M., & Hashim, U. (2016). Semiconductor Fabrication Strategy for Cycle Time and Capacity Optimization: Past and Present. In Proceedings of the 2016 International Conference on Industrial Engineering and Operations Management (No. 1, pp. 2798-2807). 
-- Wartelle, A., Dauzère-Pérès, S., Yugma, C., Christ, Q., & Roussel, R. (2025, August). Forecasting Wafer Fab Outputs using Lot Remaining Cycle Time Prediction in Semiconductor Manufacturing. In 2025 IEEE 21st International Conference on Automation Science and Engineering (CASE) (pp. 911-914). IEEE. +  * Wartelle, A., Dauzère-Pérès, S., Yugma, C., Christ, Q., & Roussel, R. (2025, August). Forecasting Wafer Fab Outputs using Lot Remaining Cycle Time Prediction in Semiconductor Manufacturing. In 2025 IEEE 21st International Conference on Automation Science and Engineering (CASE) (pp. 911-914). IEEE. 
-- Ezici, B., Costa, P., & Xu, J. (2022). Workflow Modeling and Simulation Analysis for Semiconductor Wafer Fab Manufacturing. In IISE Annual Conference. Proceedings (pp. 1-6). Institute of Industrial and Systems Engineers (IISE). +  * Ezici, B., Costa, P., & Xu, J. (2022). Workflow Modeling and Simulation Analysis for Semiconductor Wafer Fab Manufacturing. In IISE Annual Conference. Proceedings (pp. 1-6). Institute of Industrial and Systems Engineers (IISE). 
-- Semiconductor Industry Association. (2021). [Chipmakers Are Ramping Up Production to Address Semiconductor Shortage. Here’s Why that Takes Time](https://www.semiconductors.org/chipmakers-are-ramping-up-production-to-address-semiconductor-shortage-heres-why-that-takes-time/) +  * Semiconductor Industry Association. (2021). [Chipmakers Are Ramping Up Production to Address Semiconductor Shortage. Here’s Why that Takes Time](https://www.semiconductors.org/chipmakers-are-ramping-up-production-to-address-semiconductor-shortage-heres-why-that-takes-time/) 
-- Electronic Components Industry Association. (2023). [Understanding Lead Times](https://www.ecianow.org/assets/docs/Stats/LeadTimes/Understanding%20Lead%20Times.pdf) +  * Electronic Components Industry Association. (2023). [Understanding Lead Times](https://www.ecianow.org/assets/docs/Stats/LeadTimes/Understanding%20Lead%20Times.pdf) 
-- Lapedus, M. (2017). [Battling Fab Cycle Times](https://semiengineering.com/battling-fab-cycle-times/), Semiconductor Engineering. +  * Lapedus, M. (2017). [Battling Fab Cycle Times](https://semiengineering.com/battling-fab-cycle-times/), Semiconductor Engineering. 
-- Yoon, S. (2025). [From Latency to Reaction: Simulating the Next Wafer Demand Inflection](https://www.semi.org/en/blogs/from-latency-to-reaction-simulating-the-next-wafer-demand-inflection), SEMI.+  * Yoon, S. (2025). [From Latency to Reaction: Simulating the Next Wafer Demand Inflection](https://www.semi.org/en/blogs/from-latency-to-reaction-simulating-the-next-wafer-demand-inflection), SEMI.
  
 ## Yield modelling ## Yield modelling
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 According to May & Spanos, the most basic definition, is that of *manufacturing yield*. This figure 'measures the proportion of successfully fabricated products compared to the number that have started the process'. *Wafer yield* refers to wafer that get scrapped along the manufacturing process because of equipment malfunctioning, wafer transport problems, etc. Wafer yield can be measured in three ways: According to May & Spanos, the most basic definition, is that of *manufacturing yield*. This figure 'measures the proportion of successfully fabricated products compared to the number that have started the process'. *Wafer yield* refers to wafer that get scrapped along the manufacturing process because of equipment malfunctioning, wafer transport problems, etc. Wafer yield can be measured in three ways:
-- Wafer yield – the percentage of wafers that make it to final probing ; +  * Wafer yield – the percentage of wafers that make it to final probing ; 
-- Probe testing yield –the percentage of wafers that make it through the probe testing steps ; +  * Probe testing yield –the percentage of wafers that make it through the probe testing steps ; 
-- Final testing yield – the percentage of wafers that make it through the final electrical testing step. +  * Final testing yield – the percentage of wafers that make it through the final electrical testing step.
 Once a wafer successfully passed this final test, the die can be tested and define the *design yield*. This yield has two components: Once a wafer successfully passed this final test, the die can be tested and define the *design yield*. This yield has two components:
-- Functional yield (also known as “hard” or “catastrophic” yield) – the proportion of fully functional ICs ; +  * Functional yield (also known as “hard” or “catastrophic” yield) – the proportion of fully functional ICs ; 
-- Parametric yield (also known as “soft” yield) - the overall performance achieved by the functional ICs.+  * Parametric yield (also known as “soft” yield)   * the overall performance achieved by the functional ICs.
  
 The functional yield test is runned before dicing in order to avoid packaging and shipping of a defective die. The parametric yield is defined after dicing, the dies will then be separated into various performance "bins" depending of parametric variation. The functional yield test is runned before dicing in order to avoid packaging and shipping of a defective die. The parametric yield is defined after dicing, the dies will then be separated into various performance "bins" depending of parametric variation.
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 The figure below from May & Spanos summarized the different yield calculation steps. The figure below from May & Spanos summarized the different yield calculation steps.
  
-![Manufacturing process flow from the perspective of yield monitoring and control. May & Spanos](/yield-modelling.png?500)+![Manufacturing process flow from the perspective of yield monitoring and control. May & Spanos](/yield-modelling.png)
  
  
 ### Sources ### Sources
-- May, G. S., & Spanos, C. J. (2006). Fundamentals of semiconductor manufacturing and process control. John Wiley & Sons.+  * May, G. S., & Spanos, C. J. (2006). Fundamentals of semiconductor manufacturing and process control. John Wiley & Sons.
  
  
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 ![Operations in a wafer fab. Mönch et al](/cmos-process-flow.png) ![Operations in a wafer fab. Mönch et al](/cmos-process-flow.png)
  
-Going deeper, +Going deeper, Plummer et al decompose all the sub-steps that go into a photoresist deposition step for an old manufacturing process. On a more technical view, Franssila shows what happens in an epitaxy reactor, including sub-steps timing and temperature variation.
  
-Plummer et al decompose all the sub-steps that go into a photoresist deposition step for an old manufacturing process. On a more technical view, Franssila shows what happens in an epitaxy reactor, including sub-steps timing and temperature variation.+![Typical photoresist process flow for DNQ g-line and i-line positive resists. Plummer et al](/photoresist-process-flow.png?600)
  
-![Typical photoresist process flow for DNQ g-line and i-line positive resists. Plummer et al](/photoresist-process-flow.png) +![Single wafer epitaxy reactor running SiHCl3 process. Franssila](/epitaxy-process.png?600)
- +
-![Single wafer epitaxy reactor running SiHCl3 process. Franssila](/epitaxy-process.png)+
  
 On more recent technology nodes, Jung shows the different steps depending of patterning techniques for logic and DRAM devices. The looping sequences are particulary visible here and shows the complexity depending of selected processes. On more recent technology nodes, Jung shows the different steps depending of patterning techniques for logic and DRAM devices. The looping sequences are particulary visible here and shows the complexity depending of selected processes.
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 ### Sources ### Sources
-- Mönch, L., Fowler, J. W., & Mason, S. J. (2012). Production planning and control for semiconductor wafer fabrication facilities: modeling, analysis, and systems. Springer Science & Business Media. +  * Mönch, L., Fowler, J. W., & Mason, S. J. (2012). Production planning and control for semiconductor wafer fabrication facilities: modeling, analysis, and systems. Springer Science & Business Media. 
-- May, G. S., & Spanos, C. J. (2006). Fundamentals of semiconductor manufacturing and process control. John Wiley & Sons. +  * May, G. S., & Spanos, C. J. (2006). Fundamentals of semiconductor manufacturing and process control. John Wiley & Sons. 
-- Plummer, J. D. (2009). Silicon VLSI technology: fundamentals, practice and modeling. Pearson Education India. +  * Plummer, J. D. (2009). Silicon VLSI technology: fundamentals, practice and modeling. Pearson Education India. 
-- Franssila, S. (2010). Introduction to microfabrication. John Wiley & Sons. +  * Franssila, S. (2010). Introduction to microfabrication. John Wiley & Sons. 
-- Jung, E. S. (2018, December). 4 th Industrial Revolution and Boundry: Challenges and Opportunities. In 2018 IEEE International Electron Devices Meeting (IEDM) (pp. 1-1). IEEE. +  * Jung, E. S. (2018, December). 4 th Industrial Revolution and Boundry: Challenges and Opportunities. In 2018 IEEE International Electron Devices Meeting (IEDM) (pp. 1-1). IEEE.
  
  
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 Xiao provides the most detailed description of the processes used to manufacture 3D DRAM and NAND devices. Xiao provides the most detailed description of the processes used to manufacture 3D DRAM and NAND devices.
- +Such a detailed public explanation is rare to find and applies only to two types of devices for advanced technology nodes. Nevertheless, it provides a detailed understanding of the various process loops for each mask.
- +
-### Sources +
-- Xiao, H. (2016). 3D IC Devices, Technologies, and Manufacturing. SPIE press.+
  
 ### Process flow for 3D devices on DRAM ### Process flow for 3D devices on DRAM
  
 #### AA Module #### AA Module
-- Wafer clean +  * Wafer clean 
-- Pad oxidation  +  * Pad oxidation  
-- SiN hard mask deposition  +  * SiN hard mask deposition  
-- Amorphous silicon hard mask deposition +  * Amorphous silicon hard mask deposition 
-- *AA mask 1*  +  * *AA mask 1*  
-- Etch top hard mask  +  * Etch top hard mask  
-- PR strip/clean +  * PR strip/clean 
-- *AA mask 2*  +  * *AA mask 2*  
-- Etch bottom hard mask  +  * Etch bottom hard mask  
-- PR strip and clean +  * PR strip and clean 
-- Etch pad oxide +  * Etch pad oxide 
-- Etch silicon trench +  * Etch silicon trench 
-- Wafer clean +  * Wafer clean 
-- Oxidation +  * Oxidation 
-- STI oxide CVD to fill the trench  +  * STI oxide CVD to fill the trench  
-- STI oxide CMP, stop on nitride  +  * STI oxide CMP, stop on nitride  
-- Wet strip nitride and pad oxide +  * Wet strip nitride and pad oxide 
-- Wafer clean+  * Wafer clean
  
 #### Well formation #### Well formation
-- Sacrificial oxide growth +  * Sacrificial oxide growth 
-- *Cell p-well mask* +  * *Cell p-well mask* 
-- P-well implantation +  * P-well implantation 
-- N + S/D implantation +  * N + S/D implantation 
-- PR removal and clean +  * PR removal and clean 
-- *Peripheral n-well mask*  +  * *Peripheral n-well mask*  
-- N-well implantation +  * N-well implantation 
-- PMOS VT adjust implantation +  * PMOS VT adjust implantation 
-- PR removal and clean  +  * PR removal and clean  
-- *Peripheral p-well mask* +  * *Peripheral p-well mask* 
-- P-well implantation +  * P-well implantation 
-- NMOS VT adjust implantation +  * NMOS VT adjust implantation 
-- Photoresist removal and clean +  * Photoresist removal and clean 
-- Sacrificial oxide removal and clean +  * Sacrificial oxide removal and clean 
-- Rapid thermal anneal+  * Rapid thermal anneal
  
 #### BWL module #### BWL module
-- Wafer clean +  * Wafer clean 
-- Oxidation +  * Oxidation 
-- Hard-mask deposition +  * Hard-mask deposition 
-- BWL mask +  * BWL mask 
-- Etch hard mask +  * Etch hard mask 
-- BWL trench etch +  * BWL trench etch 
-- PR strip & clean +  * PR strip & clean 
-- Oxidation +  * Oxidation 
-- W and TiN etch back  +  * W and TiN etch back  
-- Wafer clean +  * Wafer clean 
-- Oxide deposition +  * Oxide deposition 
-- Oxide CMP +  * Oxide CMP 
-- Strip hard-mask +  * Strip hard-mask 
-- Oxide deposition +  * Oxide deposition 
-- TiN gate electrode deposition +  * TiN gate electrode deposition 
-- W deposition+  * W deposition
  
 #### BLC module #### BLC module
-- Wafer clean +  * Wafer clean 
-- Peripheral mask  +  * Peripheral mask  
-- Etch oxide +  * Etch oxide 
-- PR strip/clean  +  * PR strip/clean  
-- Gate oxidation and nitridation +  * Gate oxidation and nitridation 
-- Polysilicon deposition +  * Polysilicon deposition 
-- Wafer clean +  * Wafer clean 
-- PMOS poly-dope mask +  * PMOS poly-dope mask 
-- PMOS poly implantation +  * PMOS poly implantation 
-- PR strip/clean +  * PR strip/clean 
-- Array area mask +  * Array area mask 
-- Etch polysilicon +  * Etch polysilicon 
-- PR strip/clean  +  * PR strip/clean  
-- BLC mask  +  * BLC mask  
-- Etch oxide +  * Etch oxide 
-- PR strip clean  +  * PR strip clean  
-- Polysilicon deposition +  * Polysilicon deposition 
-- TiN and W deposition +  * TiN and W deposition 
-- SiN deposition +  * SiN deposition 
  
 #### BL and peripheral transistor module #### BL and peripheral transistor module
-- Wafer clean +  * Wafer clean 
-- BL mask +  * BL mask 
-- BL and peripheral gate etch +  * BL and peripheral gate etch 
-- PR strip/clean/ACI  +  * PR strip/clean/ACI  
-- Re-oxidation +  * Re-oxidation 
-- Peripheral NMOS SDE mask +  * Peripheral NMOS SDE mask 
-- Peripheral NMOS SDE implantation +  * Peripheral NMOS SDE implantation 
-- PR strip/clean +  * PR strip/clean 
-- Peripheral PMOS SDE mask +  * Peripheral PMOS SDE mask 
-- Peripheral PMOS SDE implantation +  * Peripheral PMOS SDE implantation 
-- PR strip/clean +  * PR strip/clean 
-- Spacer dielectric film deposition +  * Spacer dielectric film deposition 
-- Spacer film etch back  +  * Spacer film etch back  
-- Peripheral NMOS SD mask +  * Peripheral NMOS SD mask 
-- Peripheral NMOS SD implantation +  * Peripheral NMOS SD implantation 
-- PR strip/clean +  * PR strip/clean 
-- Peripheral PMOS SD mask +  * Peripheral PMOS SD mask 
-- Peripheral PMOS SD implantation +  * Peripheral PMOS SD implantation 
-- PR strip/clean +  * PR strip/clean 
-- RTA+  * RTA
  
  
 #### SNC, peripheral contact, and M1 process steps #### SNC, peripheral contact, and M1 process steps
-- ILD1 deposition +  * ILD1 deposition 
-- LD1 CMP +  * LD1 CMP 
-- HM deposition  +  * HM deposition  
-- SNC mask 1 +  * SNC mask 1 
-- Etch HM +  * Etch HM 
-- PR strip/clean +  * PR strip/clean 
-- SNC mask 2  +  * SNC mask 2  
-- Etch HM +  * Etch HM 
-- PR strip/clean +  * PR strip/clean 
-- Etch ILD1 +  * Etch ILD1 
-- Wafer clean +  * Wafer clean 
-- Ti/TiN/W deposition +  * Ti/TiN/W deposition 
-- W/TiN/Ti CMP +  * W/TiN/Ti CMP 
-- Etch stop layer deposition +  * Etch stop layer deposition 
-- ILD2 deposition +  * ILD2 deposition 
-- M1 mask +  * M1 mask 
-- Etch ILD2 +  * Etch ILD2 
-- PR strip/clean +  * PR strip/clean 
-- Ti/TiN/W deposition +  * Ti/TiN/W deposition 
-- W/TiN/Ti CMP +  * W/TiN/Ti CMP 
  
 #### SN module #### SN module
-- Wafer clean +  * Wafer clean 
-- Each stop layer (ESL) deposition  +  * Each stop layer (ESL) deposition  
-- ILD deposition  +  * ILD deposition  
-- SiN deposition +  * SiN deposition 
-- SN mask 1 +  * SN mask 1 
-- Etch nitride  +  * Etch nitride  
-- PR strip/clean  +  * PR strip/clean  
-- SN mask 2  +  * SN mask 2  
-- Etch nitride +  * Etch nitride 
-- PR strip/clean +  * PR strip/clean 
-- Etch oxide +  * Etch oxide 
-- TiN deposition +  * TiN deposition 
-- PR coating +  * PR coating 
-- RP etch back +  * RP etch back 
-- TiN etch +  * TiN etch 
-- SiN slot mask +  * SiN slot mask 
-- Nitride etch +  * Nitride etch 
-- PR strip/clean +  * PR strip/clean 
-- ILD removal +  * ILD removal 
-- Wafer clean +  * Wafer clean 
-- High-k film deposition +  * High-k film deposition 
-- TiN and conducting filler deposition +  * TiN and conducting filler deposition 
  
  
 #### V1 and M2 process steps #### V1 and M2 process steps
-- Peripheral area mask +  * Peripheral area mask 
-- Etch SiGe/TiN/ZAZ +  * Etch SiGe/TiN/ZAZ 
-- PR strip/clean +  * PR strip/clean 
-- ILD3 deposition +  * ILD3 deposition 
-- ILD3 CMP +  * ILD3 CMP 
-- V1 mask  +  * V1 mask  
-- V1 etch +  * V1 etch 
-- PR strip and clean +  * PR strip and clean 
-- Ti/TiN deposition +  * Ti/TiN deposition 
-- W deposition  +  * W deposition  
-- W/TiN/Ti CMP  +  * W/TiN/Ti CMP  
-- ESL deposition +  * ESL deposition 
-- ILD4 deposition  +  * ILD4 deposition  
-- M2 mask +  * M2 mask 
-- M2 etch +  * M2 etch 
-- PR strip and clean +  * PR strip and clean 
-- Barrier and seed-layer deposition +  * Barrier and seed-layer deposition 
-- Bulk copper plating +  * Bulk copper plating 
-- Cu anneal +  * Cu anneal 
-- Cu CMP+  * Cu CMP
  
 #### V2 and M3 process steps #### V2 and M3 process steps
-- ESL, ILD5, and dielectric cap deposition +  * ESL, ILD5, and dielectric cap deposition 
-- Metal HM deposition  +  * Metal HM deposition  
-- M3 mask +  * M3 mask 
-- HM etch +  * HM etch 
-- PR strip and clean +  * PR strip and clean 
-- V2 mask  +  * V2 mask  
-- Dielectric cap and ILD5 etch +  * Dielectric cap and ILD5 etch 
-- PR strip and clean +  * PR strip and clean 
-- ILD 5 etch +  * ILD 5 etch 
-- ESL removal  +  * ESL removal  
-- Clean +  * Clean 
-- Barrier and seed-layer deposition +  * Barrier and seed-layer deposition 
-- Bulk copper plating +  * Bulk copper plating 
-- Cu anneal +  * Cu anneal 
-- Cu CMP+  * Cu CMP
  
 #### V3-M4 and passivation process steps #### V3-M4 and passivation process steps
-- ESL and ILD6 deposition +  * ESL and ILD6 deposition 
-- V3 mask +  * V3 mask 
-- ILD6 and ESL etch +  * ILD6 and ESL etch 
-- Pr strip and clean +  * Pr strip and clean 
-- Ti/TiN/W deposition +  * Ti/TiN/W deposition 
-- W/TiN/Ti CMP +  * W/TiN/Ti CMP 
-- Wafer clean +  * Wafer clean 
-- Ti/Al-Cu/TiN deposition +  * Ti/Al-Cu/TiN deposition 
-- M4 mask +  * M4 mask 
-- Etch TiN/Al-Cu/Ti stack +  * Etch TiN/Al-Cu/Ti stack 
-- PR strip and clean +  * PR strip and clean 
-- Passivation oxide and nitride deposition +  * Passivation oxide and nitride deposition 
-- Bond pad mask +  * Bond pad mask 
-- Etch nitride and oxide +  * Etch nitride and oxide 
-- PR strip and clean+  * PR strip and clean
  
  
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 #### Peripheral CMOS process steps #### Peripheral CMOS process steps
--  +  * Wafer clean 
--  +  * Pad oxidation 
 +  * Nitride deposition 
 +  * AA mask 
 +  * Nitride etch 
 +  * PR strip and clean 
 +  * Silicon etch 
 +  * Wafer clean 
 +  * Oxidation 
 +  * Oxide deposition 
 +  * Oxide CMP 
 +  * Strip nitride and pad oxide and wafer clean 
 +  * Oxidation of sacrificial oxide 
 +  * n-well mask 
 +  * n-well and p-channel ion implantation 
 +  * PR strip and clean 
 +  * Strip sacrificial oxide and wafer clean 
 +  * Gate oxidation 
 +  * PolySi and silicide deposition 
 +  * Poly-dope mask 
 +  * Poly-dope ion implantation 
 +  * PR strip and clean 
 +  * Hard mask deposition 
 +  * Gate mask 
 +  * Etch hard mask 
 +  * PR strip and clean 
 +  * Etch silicide/polySi 
 +  * Wafer clean 
 +  * n-LDD mask 
 +  * n-LDD ion implantation 
 +  * PR strip and clean 
 +  * p-LDD mask 
 +  * p-LDD ion implantation 
 +  * PR strip and clean 
 +  * Spacer dielectric film CVD 
 +  * Dielectric etch back 
 +  * n-S/D mask 
 +  * n-S/D ion implantation 
 +  * PR strip and clean 
 +  * p-S/D mask 
 +  * p-S/D ion implantation 
 +  * PR strip and clean 
 +  * RTA 
 +  * SiN liner deposition 
 +  * PMD deposition
  
  
 #### Multi-layer-deposition and staircase-formation process step #### Multi-layer-deposition and staircase-formation process step
 +  * Array area mask
 +  * Etch oxide and barrier nitride
 +  * PR strip and clean
 +  * CVD oxide 1, CVD Nitride 1 and lower SG nitride
 +  * CVD oxide 2, CVD Nitride 2 and lower cell nitride
 +  * CVD oxide 3, Nitride 3 pairs
 +  * Repeating the process until Oxide N/Nitride N
 +  * CVD Oxide N+1 and cap oxide
 +  * First staircase mask
 +  * Etch Oxide N+1/Nitride N, stop on Oxide N
 +  * PR trimming
 +  * Etch Oxide N/Nitride N-1, stop on Oxide N-1
 +  * PR trimming
 +  * Etch Oxide N-1/Nitride N-2, stop on Oxide N-2
 +  * *Repeating trimming and O/N pair etch*
 +  * PR strip and clean
 +  * *Second staircase mask*
 +  * *Repeating trimming and O/N pair etch*
 +  * *Third staircase mask*
 +  * *Repeating trimming and O/N pair etch*
 +  * Etch Oxide 1, stop on silicon
 +  * PR strip and wafer clean
 +  * Oxide CVD
 +  * Oxide CMP
 +
 +
 +#### 3D NAND channel formation process steps
 +  * Channel mask
 +  * Etch hard mask
 +  * Etch multi-layers
 +  * Remove hard mask and wafer clean
 +  * SEG Si
 +  * Deposit high-k dielectric
 +  * Deposit charge trap nitride
 +  * Deposit gate oxide
 +  * Etch back channel dielectric layers
 +  * Wafer clean
 +  * Deposit polySi channel
 +  * Deposit silicon oxide filler
 +  * Oxide recess
 +  * Deposit polySi
 +  * PolySi CMP
 +  * Post-CMP clean
 +
 +
 +#### Process steps for the isolation module of 3D-NAND
 +  * Wafer clean
 +  * Isolation mask
 +  * Etch hard mask
 +  * Etch trenches in ONON multi-layers and stop on silicon
 +  * Remove hard mask
 +  * Remove nitride layers
 +  * Wafer clean
 +  * Oxidation of SEG
 +  * TiN deposition
 +  * W deposition
 +  * Trench W removal
 +  * Trench TiN removal
 +  * Wafer clean
 +  * Oxide deposition
 +  * Oxide etch back
 +  * TiN deposition
 +  * W deposition
 +  * W CMP
 +  * Oxide cap deposition
 +
 +#### Process steps of the contact and interconnect module of 3D-NAND
 +  * Wafer clean
 +  * First contact mask
 +  * Etch hard mask
 +  * Etch shallower staircase contacts
 +  * Strip PR and wafer clean
 +  * *Apply the second contact mask and etch staircase contacts*
 +  * Strip PR and wafer clean
 +  * *Repeating staircase contact litho, etch and clean*
 +  * Remove hard mask and wafer clean
 +  * TiN liner deposition
 +  * W deposition
 +  * W CMP
 +  * Wafer clean
 +  * Oxide CVD
 +  * V1 mask
 +  * V1 etch, PR strip, and clean
 +  * Oxide CVD
 +  * M1 mask
 +  * M1 etch, PR strip, and clean
 +  * TiN deposition, W CVD and W CMP
 +  * Oxide CVD
 +  * V2 mask
 +  * V2 etch, PR strip, and clean
 +  * TiN deposition, W CVD, W CMP
 +  * Oxide CVD
 +  * M2 mask
 +  * M2 etch, PR strip, and clean
 +  * TaN deposition, Cu seed deposition, Cu plating, Cu anneal and Cu CMP
 +  * Oxide CVD
 +  * V3 mask
 +  * V3 etch, PR strip, and clean
 +  * TiN deposition, W CVD, W CMP
 +  * PVD TiN, PVD Al-Cu and PVD TiN
 +  * M3 mask
 +  * M3 etch TiN/W/TiN metal stack, PR strip and clean
 +  * Oxide CVD and nitride CVD
 +  * Bond pad mask
 +  * Etch nitride/oxide
 +  * PR strip and clean
 +
 +
 +### Sources
 +  * Xiao, H. (2016). 3D IC Devices, Technologies, and Manufacturing. SPIE press.
 +
 +
 +
 +
  
  
  
  
-#### 3D NAND channel formation process steps 
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