fab-process-flow.md
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| fab-process-flow.md [2026/03/24 15:52] – gauthier.roussilhe.ext | fab-process-flow.md [2026/03/27 09:58] (current) – [Full process flow for memory devices] gauthier.roussilhe.ext | ||
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| - | # Semiconductor | + | # Front-end |
| Semiconductor manufacturing is among the most complex processes on Earth, if not the most complex. Summarizing the process flow of such an industry in simple terms is difficult given the specific requirements of each type of product produced. | Semiconductor manufacturing is among the most complex processes on Earth, if not the most complex. Summarizing the process flow of such an industry in simple terms is difficult given the specific requirements of each type of product produced. | ||
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| In addition to the various constraints on productivity, | In addition to the various constraints on productivity, | ||
| - | According to May & Spanos, the most basic definition, is that of *manufacturing yield*. This figure ' | + | According to May & Spanos, the most basic definition, is that of *manufacturing yield*. This figure ' |
| * Wafer yield – the percentage of wafers that make it to final probing ; | * Wafer yield – the percentage of wafers that make it to final probing ; | ||
| * Probe testing yield –the percentage of wafers that make it through the probe testing steps ; | * Probe testing yield –the percentage of wafers that make it through the probe testing steps ; | ||
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| * Franssila, S. (2010). Introduction to microfabrication. John Wiley & Sons. | * Franssila, S. (2010). Introduction to microfabrication. John Wiley & Sons. | ||
| * Jung, E. S. (2018, December). 4 th Industrial Revolution and Boundry: Challenges and Opportunities. In 2018 IEEE International Electron Devices Meeting (IEDM) (pp. 1-1). IEEE. | * Jung, E. S. (2018, December). 4 th Industrial Revolution and Boundry: Challenges and Opportunities. In 2018 IEEE International Electron Devices Meeting (IEDM) (pp. 1-1). IEEE. | ||
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| Xiao provides the most detailed description of the processes used to manufacture 3D DRAM and NAND devices. | Xiao provides the most detailed description of the processes used to manufacture 3D DRAM and NAND devices. | ||
| Such a detailed public explanation is rare to find and applies only to two types of devices for advanced technology nodes. Nevertheless, | Such a detailed public explanation is rare to find and applies only to two types of devices for advanced technology nodes. Nevertheless, | ||
| - | |||
| - | ### Sources | ||
| - | * Xiao, H. (2016). 3D IC Devices, Technologies, | ||
| ### Process flow for 3D devices on DRAM | ### Process flow for 3D devices on DRAM | ||
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| * SiN hard mask deposition | * SiN hard mask deposition | ||
| * Amorphous silicon hard mask deposition | * Amorphous silicon hard mask deposition | ||
| - | * *AA mask 1 * | + | * *AA mask 1* |
| * Etch top hard mask | * Etch top hard mask | ||
| * PR strip/clean | * PR strip/clean | ||
| - | * *AA mask 2 * | + | * *AA mask 2* |
| * Etch bottom hard mask | * Etch bottom hard mask | ||
| * PR strip and clean | * PR strip and clean | ||
| Line 127: | Line 123: | ||
| * N + S/D implantation | * N + S/D implantation | ||
| * PR removal and clean | * PR removal and clean | ||
| - | * *Peripheral n-well mask * | + | * *Peripheral n-well mask* |
| * N-well implantation | * N-well implantation | ||
| * PMOS VT adjust implantation | * PMOS VT adjust implantation | ||
| Line 358: | Line 354: | ||
| * Etch oxide and barrier nitride | * Etch oxide and barrier nitride | ||
| * PR strip and clean | * PR strip and clean | ||
| - | * CVD oxide_1, CVD Nitride_1 | + | * CVD oxide 1, CVD Nitride 1 and lower SG nitride |
| - | * CVD oxide_2, CVD Nitride_2 | + | * CVD oxide 2, CVD Nitride 2 and lower cell nitride |
| - | * CVD oxide_3, Nitride_3 | + | * CVD oxide 3, Nitride 3 pairs |
| - | | + | * Repeating the process until Oxide N/Nitride N |
| - | * CVD Oxide_N+1 and cap oxide | + | * CVD Oxide N+1 and cap oxide |
| * First staircase mask | * First staircase mask | ||
| - | * Etch Oxide_N+1/Nitride_N, stop on Oxide_N | + | * Etch Oxide N+1/Nitride N, stop on Oxide N |
| * PR trimming | * PR trimming | ||
| - | * Etch Oxide_N/Nitride_N-1, stop on Oxide_N-1 | + | * Etch Oxide N/Nitride N-1, stop on Oxide N-1 |
| * PR trimming | * PR trimming | ||
| - | * Etch Oxide_N-1/Nitride_N-2, stop on Oxide_N-2 | + | * Etch Oxide N-1/Nitride N-2, stop on Oxide N-2 |
| * *Repeating trimming and O/N pair etch* | * *Repeating trimming and O/N pair etch* | ||
| * PR strip and clean | * PR strip and clean | ||
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| * *Third staircase mask* | * *Third staircase mask* | ||
| * *Repeating trimming and O/N pair etch* | * *Repeating trimming and O/N pair etch* | ||
| - | * Etch Oxide_1, stop on silicon | + | * Etch Oxide 1, stop on silicon |
| * PR strip and wafer clean | * PR strip and wafer clean | ||
| * Oxide CVD | * Oxide CVD | ||
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| - | + | ### Sources | |
| + | * Xiao, H. (2016). 3D IC Devices, Technologies, | ||
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