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| fab-process-flow.md [2026/05/13 15:26] – [Full process flow for memory devices] gauthier.roussilhe.ext | fab-process-flow.md [2026/05/13 16:53] (current) – [Sources] gauthier.roussilhe.ext | ||
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| New advanced nodes (logic and memory) put an additional strain on fab production. According to SEMI : "since 2020, fab cycle times have grown at a compound annual growth rate of 14.8%. This represents a fundamental deceleration in fab throughput, meaning that even with the same number of tools and consistent utilization rates, the volume of wafers that can be processed is now structurally constrained." | New advanced nodes (logic and memory) put an additional strain on fab production. According to SEMI : "since 2020, fab cycle times have grown at a compound annual growth rate of 14.8%. This represents a fundamental deceleration in fab throughput, meaning that even with the same number of tools and consistent utilization rates, the volume of wafers that can be processed is now structurally constrained." | ||
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| ### Sources | ### Sources | ||
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| * Lapedus, M. (2017). [Battling Fab Cycle Times](https:// | * Lapedus, M. (2017). [Battling Fab Cycle Times](https:// | ||
| * Yoon, S. (2025). [From Latency to Reaction: Simulating the Next Wafer Demand Inflection](https:// | * Yoon, S. (2025). [From Latency to Reaction: Simulating the Next Wafer Demand Inflection](https:// | ||
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| ## Yield modelling | ## Yield modelling | ||
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| The figure below from May & Spanos summarized the different yield calculation steps. | The figure below from May & Spanos summarized the different yield calculation steps. | ||
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| ### Sources | ### Sources | ||
| * May, G. S., & Spanos, C. J. (2006). Fundamentals of semiconductor manufacturing and process control. John Wiley & Sons. | * May, G. S., & Spanos, C. J. (2006). Fundamentals of semiconductor manufacturing and process control. John Wiley & Sons. | ||
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| The process flow can be summarized in different ways. From a fab operations perspective, | The process flow can be summarized in different ways. From a fab operations perspective, | ||
| - |  | + | {{:cmos-process-flow.png?800|}} |
| - | Going deeper, Plummer et al decompose all the sub-steps that go into a photoresist deposition step for an old manufacturing process. On a more technical view, Franssila shows what happens in an epitaxy reactor, including sub-steps timing and temperature variation. | ||
| - | . Introduction to microfabrication. John Wiley & Sons. | * Franssila, S. (2010). Introduction to microfabrication. John Wiley & Sons. | ||
| * Jung, E. S. (2018, December). 4 th Industrial Revolution and Boundry: Challenges and Opportunities. In 2018 IEEE International Electron Devices Meeting (IEDM) (pp. 1-1). IEEE. | * Jung, E. S. (2018, December). 4 th Industrial Revolution and Boundry: Challenges and Opportunities. In 2018 IEEE International Electron Devices Meeting (IEDM) (pp. 1-1). IEEE. | ||
| - | |||
| - | ## Full process flow for memory devices | ||
| - | |||
| - | Xiao provides the most detailed description of the processes used to manufacture 3D DRAM and NAND devices. | ||
| - | Such a detailed public explanation is rare to find and applies only to two types of devices for advanced technology nodes. Nevertheless, | ||
| - | |||
| - | ### Process flow for 3D devices on DRAM | ||
| - | |||
| - | #### AA Module | ||
| - | * Wafer clean | ||
| - | * Pad oxidation | ||
| - | * SiN hard mask deposition | ||
| - | * Amorphous silicon hard mask deposition | ||
| - | * *AA mask 1* | ||
| - | * Etch top hard mask | ||
| - | * PR strip/clean | ||
| - | * *AA mask 2* | ||
| - | * Etch bottom hard mask | ||
| - | * PR strip and clean | ||
| - | * Etch pad oxide | ||
| - | * Etch silicon trench | ||
| - | * Wafer clean | ||
| - | * Oxidation | ||
| - | * STI oxide CVD to fill the trench | ||
| - | * STI oxide CMP, stop on nitride | ||
| - | * Wet strip nitride and pad oxide | ||
| - | * Wafer clean | ||
| - | |||
| - | #### Well formation | ||
| - | * Sacrificial oxide growth | ||
| - | * *Cell p-well mask* | ||
| - | * P-well implantation | ||
| - | * N + S/D implantation | ||
| - | * PR removal and clean | ||
| - | * *Peripheral n-well mask* | ||
| - | * N-well implantation | ||
| - | * PMOS VT adjust implantation | ||
| - | * PR removal and clean | ||
| - | * *Peripheral p-well mask* | ||
| - | * P-well implantation | ||
| - | * NMOS VT adjust implantation | ||
| - | * Photoresist removal and clean | ||
| - | * Sacrificial oxide removal and clean | ||
| - | * Rapid thermal anneal | ||
| - | |||
| - | #### BWL module | ||
| - | * Wafer clean | ||
| - | * Oxidation | ||
| - | * Hard-mask deposition | ||
| - | * BWL mask | ||
| - | * Etch hard mask | ||
| - | * BWL trench etch | ||
| - | * PR strip & clean | ||
| - | * Oxidation | ||
| - | * W and TiN etch back | ||
| - | * Wafer clean | ||
| - | * Oxide deposition | ||
| - | * Oxide CMP | ||
| - | * Strip hard-mask | ||
| - | * Oxide deposition | ||
| - | * TiN gate electrode deposition | ||
| - | * W deposition | ||
| - | |||
| - | #### BLC module | ||
| - | * Wafer clean | ||
| - | * Peripheral mask | ||
| - | * Etch oxide | ||
| - | * PR strip/ | ||
| - | * Gate oxidation and nitridation | ||
| - | * Polysilicon deposition | ||
| - | * Wafer clean | ||
| - | * PMOS poly-dope mask | ||
| - | * PMOS poly implantation | ||
| - | * PR strip/clean | ||
| - | * Array area mask | ||
| - | * Etch polysilicon | ||
| - | * PR strip/ | ||
| - | * BLC mask | ||
| - | * Etch oxide | ||
| - | * PR strip clean | ||
| - | * Polysilicon deposition | ||
| - | * TiN and W deposition | ||
| - | * SiN deposition | ||
| - | |||
| - | #### BL and peripheral transistor module | ||
| - | * Wafer clean | ||
| - | * BL mask | ||
| - | * BL and peripheral gate etch | ||
| - | * PR strip/ | ||
| - | * Re-oxidation | ||
| - | * Peripheral NMOS SDE mask | ||
| - | * Peripheral NMOS SDE implantation | ||
| - | * PR strip/clean | ||
| - | * Peripheral PMOS SDE mask | ||
| - | * Peripheral PMOS SDE implantation | ||
| - | * PR strip/clean | ||
| - | * Spacer dielectric film deposition | ||
| - | * Spacer film etch back | ||
| - | * Peripheral NMOS SD mask | ||
| - | * Peripheral NMOS SD implantation | ||
| - | * PR strip/clean | ||
| - | * Peripheral PMOS SD mask | ||
| - | * Peripheral PMOS SD implantation | ||
| - | * PR strip/clean | ||
| - | * RTA | ||
| - | |||
| - | |||
| - | #### SNC, peripheral contact, and M1 process steps | ||
| - | * ILD1 deposition | ||
| - | * LD1 CMP | ||
| - | * HM deposition | ||
| - | * SNC mask 1 | ||
| - | * Etch HM | ||
| - | * PR strip/clean | ||
| - | * SNC mask 2 | ||
| - | * Etch HM | ||
| - | * PR strip/clean | ||
| - | * Etch ILD1 | ||
| - | * Wafer clean | ||
| - | * Ti/TiN/W deposition | ||
| - | * W/TiN/Ti CMP | ||
| - | * Etch stop layer deposition | ||
| - | * ILD2 deposition | ||
| - | * M1 mask | ||
| - | * Etch ILD2 | ||
| - | * PR strip/clean | ||
| - | * Ti/TiN/W deposition | ||
| - | * W/TiN/Ti CMP | ||
| - | |||
| - | #### SN module | ||
| - | * Wafer clean | ||
| - | * Each stop layer (ESL) deposition | ||
| - | * ILD deposition | ||
| - | * SiN deposition | ||
| - | * SN mask 1 | ||
| - | * Etch nitride | ||
| - | * PR strip/ | ||
| - | * SN mask 2 | ||
| - | * Etch nitride | ||
| - | * PR strip/clean | ||
| - | * Etch oxide | ||
| - | * TiN deposition | ||
| - | * PR coating | ||
| - | * RP etch back | ||
| - | * TiN etch | ||
| - | * SiN slot mask | ||
| - | * Nitride etch | ||
| - | * PR strip/clean | ||
| - | * ILD removal | ||
| - | * Wafer clean | ||
| - | * High-k film deposition | ||
| - | * TiN and conducting filler deposition | ||
| - | |||
| - | |||
| - | #### V1 and M2 process steps | ||
| - | * Peripheral area mask | ||
| - | * Etch SiGe/ | ||
| - | * PR strip/clean | ||
| - | * ILD3 deposition | ||
| - | * ILD3 CMP | ||
| - | * V1 mask | ||
| - | * V1 etch | ||
| - | * PR strip and clean | ||
| - | * Ti/TiN deposition | ||
| - | * W deposition | ||
| - | * W/TiN/Ti CMP | ||
| - | * ESL deposition | ||
| - | * ILD4 deposition | ||
| - | * M2 mask | ||
| - | * M2 etch | ||
| - | * PR strip and clean | ||
| - | * Barrier and seed-layer deposition | ||
| - | * Bulk copper plating | ||
| - | * Cu anneal | ||
| - | * Cu CMP | ||
| - | |||
| - | #### V2 and M3 process steps | ||
| - | * ESL, ILD5, and dielectric cap deposition | ||
| - | * Metal HM deposition | ||
| - | * M3 mask | ||
| - | * HM etch | ||
| - | * PR strip and clean | ||
| - | * V2 mask | ||
| - | * Dielectric cap and ILD5 etch | ||
| - | * PR strip and clean | ||
| - | * ILD 5 etch | ||
| - | * ESL removal | ||
| - | * Clean | ||
| - | * Barrier and seed-layer deposition | ||
| - | * Bulk copper plating | ||
| - | * Cu anneal | ||
| - | * Cu CMP | ||
| - | |||
| - | #### V3-M4 and passivation process steps | ||
| - | * ESL and ILD6 deposition | ||
| - | * V3 mask | ||
| - | * ILD6 and ESL etch | ||
| - | * Pr strip and clean | ||
| - | * Ti/TiN/W deposition | ||
| - | * W/TiN/Ti CMP | ||
| - | * Wafer clean | ||
| - | * Ti/ | ||
| - | * M4 mask | ||
| - | * Etch TiN/ | ||
| - | * PR strip and clean | ||
| - | * Passivation oxide and nitride deposition | ||
| - | * Bond pad mask | ||
| - | * Etch nitride and oxide | ||
| - | * PR strip and clean | ||
| - | |||
| - | ### Process flow for 3D-NAND Flash | ||
| - | |||
| - | #### Peripheral CMOS process steps | ||
| - | * Wafer clean | ||
| - | * Pad oxidation | ||
| - | * Nitride deposition | ||
| - | * AA mask | ||
| - | * Nitride etch | ||
| - | * PR strip and clean | ||
| - | * Silicon etch | ||
| - | * Wafer clean | ||
| - | * Oxidation | ||
| - | * Oxide deposition | ||
| - | * Oxide CMP | ||
| - | * Strip nitride and pad oxide and wafer clean | ||
| - | * Oxidation of sacrificial oxide | ||
| - | * n-well mask | ||
| - | * n-well and p-channel ion implantation | ||
| - | * PR strip and clean | ||
| - | * Strip sacrificial oxide and wafer clean | ||
| - | * Gate oxidation | ||
| - | * PolySi and silicide deposition | ||
| - | * Poly-dope mask | ||
| - | * Poly-dope ion implantation | ||
| - | * PR strip and clean | ||
| - | * Hard mask deposition | ||
| - | * Gate mask | ||
| - | * Etch hard mask | ||
| - | * PR strip and clean | ||
| - | * Etch silicide/ | ||
| - | * Wafer clean | ||
| - | * n-LDD mask | ||
| - | * n-LDD ion implantation | ||
| - | * PR strip and clean | ||
| - | * p-LDD mask | ||
| - | * p-LDD ion implantation | ||
| - | * PR strip and clean | ||
| - | * Spacer dielectric film CVD | ||
| - | * Dielectric etch back | ||
| - | * n-S/D mask | ||
| - | * n-S/D ion implantation | ||
| - | * PR strip and clean | ||
| - | * p-S/D mask | ||
| - | * p-S/D ion implantation | ||
| - | * PR strip and clean | ||
| - | * RTA | ||
| - | * SiN liner deposition | ||
| - | * PMD deposition | ||
| - | |||
| - | |||
| - | #### Multi-layer-deposition and staircase-formation process step | ||
| - | * Array area mask | ||
| - | * Etch oxide and barrier nitride | ||
| - | * PR strip and clean | ||
| - | * CVD oxide 1, CVD Nitride 1 and lower SG nitride | ||
| - | * CVD oxide 2, CVD Nitride 2 and lower cell nitride | ||
| - | * CVD oxide 3, Nitride 3 pairs | ||
| - | * Repeating the process until Oxide N/Nitride N | ||
| - | * CVD Oxide N+1 and cap oxide | ||
| - | * First staircase mask | ||
| - | * Etch Oxide N+1/Nitride N, stop on Oxide N | ||
| - | * PR trimming | ||
| - | * Etch Oxide N/Nitride N-1, stop on Oxide N-1 | ||
| - | * PR trimming | ||
| - | * Etch Oxide N-1/Nitride N-2, stop on Oxide N-2 | ||
| - | * *Repeating trimming and O/N pair etch* | ||
| - | * PR strip and clean | ||
| - | * *Second staircase mask* | ||
| - | * *Repeating trimming and O/N pair etch* | ||
| - | * *Third staircase mask* | ||
| - | * *Repeating trimming and O/N pair etch* | ||
| - | * Etch Oxide 1, stop on silicon | ||
| - | * PR strip and wafer clean | ||
| - | * Oxide CVD | ||
| - | * Oxide CMP | ||
| - | |||
| - | |||
| - | #### 3D NAND channel formation process steps | ||
| - | * Channel mask | ||
| - | * Etch hard mask | ||
| - | * Etch multi-layers | ||
| - | * Remove hard mask and wafer clean | ||
| - | * SEG Si | ||
| - | * Deposit high-k dielectric | ||
| - | * Deposit charge trap nitride | ||
| - | * Deposit gate oxide | ||
| - | * Etch back channel dielectric layers | ||
| - | * Wafer clean | ||
| - | * Deposit polySi channel | ||
| - | * Deposit silicon oxide filler | ||
| - | * Oxide recess | ||
| - | * Deposit polySi | ||
| - | * PolySi CMP | ||
| - | * Post-CMP clean | ||
| - | |||
| - | |||
| - | #### Process steps for the isolation module of 3D-NAND | ||
| - | * Wafer clean | ||
| - | * Isolation mask | ||
| - | * Etch hard mask | ||
| - | * Etch trenches in ONON multi-layers and stop on silicon | ||
| - | * Remove hard mask | ||
| - | * Remove nitride layers | ||
| - | * Wafer clean | ||
| - | * Oxidation of SEG | ||
| - | * TiN deposition | ||
| - | * W deposition | ||
| - | * Trench W removal | ||
| - | * Trench TiN removal | ||
| - | * Wafer clean | ||
| - | * Oxide deposition | ||
| - | * Oxide etch back | ||
| - | * TiN deposition | ||
| - | * W deposition | ||
| - | * W CMP | ||
| - | * Oxide cap deposition | ||
| - | |||
| - | #### Process steps of the contact and interconnect module of 3D-NAND | ||
| - | * Wafer clean | ||
| - | * First contact mask | ||
| - | * Etch hard mask | ||
| - | * Etch shallower staircase contacts | ||
| - | * Strip PR and wafer clean | ||
| - | * *Apply the second contact mask and etch staircase contacts* | ||
| - | * Strip PR and wafer clean | ||
| - | * *Repeating staircase contact litho, etch and clean* | ||
| - | * Remove hard mask and wafer clean | ||
| - | * TiN liner deposition | ||
| - | * W deposition | ||
| - | * W CMP | ||
| - | * Wafer clean | ||
| - | * Oxide CVD | ||
| - | * V1 mask | ||
| - | * V1 etch, PR strip, and clean | ||
| - | * Oxide CVD | ||
| - | * M1 mask | ||
| - | * M1 etch, PR strip, and clean | ||
| - | * TiN deposition, W CVD and W CMP | ||
| - | * Oxide CVD | ||
| - | * V2 mask | ||
| - | * V2 etch, PR strip, and clean | ||
| - | * TiN deposition, W CVD, W CMP | ||
| - | * Oxide CVD | ||
| - | * M2 mask | ||
| - | * M2 etch, PR strip, and clean | ||
| - | * TaN deposition, Cu seed deposition, Cu plating, Cu anneal and Cu CMP | ||
| - | * Oxide CVD | ||
| - | * V3 mask | ||
| - | * V3 etch, PR strip, and clean | ||
| - | * TiN deposition, W CVD, W CMP | ||
| - | * PVD TiN, PVD Al-Cu and PVD TiN | ||
| - | * M3 mask | ||
| - | * M3 etch TiN/W/TiN metal stack, PR strip and clean | ||
| - | * Oxide CVD and nitride CVD | ||
| - | * Bond pad mask | ||
| - | * Etch nitride/ | ||
| - | * PR strip and clean | ||
| - | |||
| - | |||
| - | ### Sources | ||
| - | * Xiao, H. (2016). 3D IC Devices, Technologies, | ||
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