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fab-process-flow.md [2026/05/13 15:55] – [Process flow for 3D devices on DRAM] gauthier.roussilhe.extfab-process-flow.md [2026/05/13 16:53] (current) – [Sources] gauthier.roussilhe.ext
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 New advanced nodes (logic and memory) put an additional strain on fab production. According to SEMI : "since 2020, fab cycle times have grown at a compound annual growth rate of 14.8%. This represents a fundamental deceleration in fab throughput, meaning that even with the same number of tools and consistent utilization rates, the volume of wafers that can be processed is now structurally constrained." They point this growth to "rising process complexity, increased equipment density, and tighter quality control requirements" (equipment spending per wafer area has surged over 150% since 2020). In the case of advanced memory, SEMI notes that "HBM wafers consume over three times more wafer area per bit compared to standard DRAM, creating potentially significant wafer demand." New advanced nodes (logic and memory) put an additional strain on fab production. According to SEMI : "since 2020, fab cycle times have grown at a compound annual growth rate of 14.8%. This represents a fundamental deceleration in fab throughput, meaning that even with the same number of tools and consistent utilization rates, the volume of wafers that can be processed is now structurally constrained." They point this growth to "rising process complexity, increased equipment density, and tighter quality control requirements" (equipment spending per wafer area has surged over 150% since 2020). In the case of advanced memory, SEMI notes that "HBM wafers consume over three times more wafer area per bit compared to standard DRAM, creating potentially significant wafer demand."
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 ### Sources ### Sources
  
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   * Lapedus, M. (2017). [Battling Fab Cycle Times](https://semiengineering.com/battling-fab-cycle-times/), Semiconductor Engineering.   * Lapedus, M. (2017). [Battling Fab Cycle Times](https://semiengineering.com/battling-fab-cycle-times/), Semiconductor Engineering.
   * Yoon, S. (2025). [From Latency to Reaction: Simulating the Next Wafer Demand Inflection](https://www.semi.org/en/blogs/from-latency-to-reaction-simulating-the-next-wafer-demand-inflection), SEMI.   * Yoon, S. (2025). [From Latency to Reaction: Simulating the Next Wafer Demand Inflection](https://www.semi.org/en/blogs/from-latency-to-reaction-simulating-the-next-wafer-demand-inflection), SEMI.
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 ## Yield modelling ## Yield modelling
  
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 The figure below from May & Spanos summarized the different yield calculation steps. The figure below from May & Spanos summarized the different yield calculation steps.
  
-![Manufacturing process flow from the perspective of yield monitoring and control. May & Spanos](/yield-modelling.png) +{{:yield-modelling.png?800|Manufacturing process flow from the perspective of yield monitoring and control. May & Spanos}} 
- +)
 ### Sources ### Sources
   * May, G. S., & Spanos, C. J. (2006). Fundamentals of semiconductor manufacturing and process control. John Wiley & Sons.   * May, G. S., & Spanos, C. J. (2006). Fundamentals of semiconductor manufacturing and process control. John Wiley & Sons.
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 The process flow can be summarized in different ways. From a fab operations perspective, Mönch et al provide a simple view of the looping dynamics on front-end processes. The process flow can be summarized in different ways. From a fab operations perspective, Mönch et al provide a simple view of the looping dynamics on front-end processes.
  
-![Operations in a wafer fab. Mönch et al](/wafer-fab-flow.png)+{{:wafer-fab-flow.png?800|Operations in a wafer fab. Mönch et al}}
  
 May and Spanos propose a simplified process flow for a planar CMOS, a simpler flow compared to today's 3D structures. May and Spanos propose a simplified process flow for a planar CMOS, a simpler flow compared to today's 3D structures.
  
-![Operations in a wafer fab. Mönch et al](/cmos-process-flow.png)+{{:cmos-process-flow.png?800|}}
  
-Going deeper, Plummer et al decompose all the sub-steps that go into a photoresist deposition step for an old manufacturing process. On a more technical view, Franssila shows what happens in an epitaxy reactor, including sub-steps timing and temperature variation. 
  
-![Typical photoresist process flow for DNQ g-line and i-line positive resists. Plummer et al](/photoresist-process-flow.png?600)+Going deeper, Plummer et al decompose all the sub-steps that go into a photoresist deposition step for an old manufacturing process. On a more technical view, Franssila shows what happens in an epitaxy reactor, including sub-steps timing and temperature variation.
  
-![Single wafer epitaxy reactor running SiHCl3 process. Franssila](/epitaxy-process.png?600)+{{:wafer-fig-03.jpg?800|Left: typical photoresist process flow for DNQ g-line and i-line positive resists. Plummer et al. Right: single wafer epitaxy reactor running SiHCl3 process. Franssila}}
  
 On more recent technology nodes, Jung shows the different steps depending of patterning techniques for logic and DRAM devices. The looping sequences are particulary visible here and shows the complexity depending of selected processes. On more recent technology nodes, Jung shows the different steps depending of patterning techniques for logic and DRAM devices. The looping sequences are particulary visible here and shows the complexity depending of selected processes.
  
-![Operations in a wafer fab. Mönch et al](/patterning.png)+{{:patterning.png?800|}} 
 + 
 +More comprehensive process flows have been explored for [[dram-case.md|3D devices on RAM]] and [[3dnand-case.md|3D NAND Flash]].
  
 ### Sources ### Sources
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   * Franssila, S. (2010). Introduction to microfabrication. John Wiley & Sons.   * Franssila, S. (2010). Introduction to microfabrication. John Wiley & Sons.
   * Jung, E. S. (2018, December). 4 th Industrial Revolution and Boundry: Challenges and Opportunities. In 2018 IEEE International Electron Devices Meeting (IEDM) (pp. 1-1). IEEE.   * Jung, E. S. (2018, December). 4 th Industrial Revolution and Boundry: Challenges and Opportunities. In 2018 IEEE International Electron Devices Meeting (IEDM) (pp. 1-1). IEEE.
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-## Full process flow for memory devices 
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-Xiao provides the most detailed description of the processes used to manufacture 3D DRAM and NAND devices. 
-Such a detailed public explanation is rare to find and applies only to two types of devices for advanced technology nodes. Nevertheless, it provides a detailed understanding of the various process loops for each mask. 
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-### Process flow for 3D-NAND Flash 
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-#### Peripheral CMOS process steps 
-  * Wafer clean 
-  * Pad oxidation 
-  * Nitride deposition 
-  * AA mask 
-  * Nitride etch 
-  * PR strip and clean 
-  * Silicon etch 
-  * Wafer clean 
-  * Oxidation 
-  * Oxide deposition 
-  * Oxide CMP 
-  * Strip nitride and pad oxide and wafer clean 
-  * Oxidation of sacrificial oxide 
-  * n-well mask 
-  * n-well and p-channel ion implantation 
-  * PR strip and clean 
-  * Strip sacrificial oxide and wafer clean 
-  * Gate oxidation 
-  * PolySi and silicide deposition 
-  * Poly-dope mask 
-  * Poly-dope ion implantation 
-  * PR strip and clean 
-  * Hard mask deposition 
-  * Gate mask 
-  * Etch hard mask 
-  * PR strip and clean 
-  * Etch silicide/polySi 
-  * Wafer clean 
-  * n-LDD mask 
-  * n-LDD ion implantation 
-  * PR strip and clean 
-  * p-LDD mask 
-  * p-LDD ion implantation 
-  * PR strip and clean 
-  * Spacer dielectric film CVD 
-  * Dielectric etch back 
-  * n-S/D mask 
-  * n-S/D ion implantation 
-  * PR strip and clean 
-  * p-S/D mask 
-  * p-S/D ion implantation 
-  * PR strip and clean 
-  * RTA 
-  * SiN liner deposition 
-  * PMD deposition 
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-#### Multi-layer-deposition and staircase-formation process step 
-  * Array area mask 
-  * Etch oxide and barrier nitride 
-  * PR strip and clean 
-  * CVD oxide 1, CVD Nitride 1 and lower SG nitride 
-  * CVD oxide 2, CVD Nitride 2 and lower cell nitride 
-  * CVD oxide 3, Nitride 3 pairs 
-  * Repeating the process until Oxide N/Nitride N 
-  * CVD Oxide N+1 and cap oxide 
-  * First staircase mask 
-  * Etch Oxide N+1/Nitride N, stop on Oxide N 
-  * PR trimming 
-  * Etch Oxide N/Nitride N-1, stop on Oxide N-1 
-  * PR trimming 
-  * Etch Oxide N-1/Nitride N-2, stop on Oxide N-2 
-  * *Repeating trimming and O/N pair etch* 
-  * PR strip and clean 
-  * *Second staircase mask* 
-  * *Repeating trimming and O/N pair etch* 
-  * *Third staircase mask* 
-  * *Repeating trimming and O/N pair etch* 
-  * Etch Oxide 1, stop on silicon 
-  * PR strip and wafer clean 
-  * Oxide CVD 
-  * Oxide CMP 
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- 
-#### 3D NAND channel formation process steps 
-  * Channel mask 
-  * Etch hard mask 
-  * Etch multi-layers 
-  * Remove hard mask and wafer clean 
-  * SEG Si 
-  * Deposit high-k dielectric 
-  * Deposit charge trap nitride 
-  * Deposit gate oxide 
-  * Etch back channel dielectric layers 
-  * Wafer clean 
-  * Deposit polySi channel 
-  * Deposit silicon oxide filler 
-  * Oxide recess 
-  * Deposit polySi 
-  * PolySi CMP 
-  * Post-CMP clean 
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-#### Process steps for the isolation module of 3D-NAND 
-  * Wafer clean 
-  * Isolation mask 
-  * Etch hard mask 
-  * Etch trenches in ONON multi-layers and stop on silicon 
-  * Remove hard mask 
-  * Remove nitride layers 
-  * Wafer clean 
-  * Oxidation of SEG 
-  * TiN deposition 
-  * W deposition 
-  * Trench W removal 
-  * Trench TiN removal 
-  * Wafer clean 
-  * Oxide deposition 
-  * Oxide etch back 
-  * TiN deposition 
-  * W deposition 
-  * W CMP 
-  * Oxide cap deposition 
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-#### Process steps of the contact and interconnect module of 3D-NAND 
-  * Wafer clean 
-  * First contact mask 
-  * Etch hard mask 
-  * Etch shallower staircase contacts 
-  * Strip PR and wafer clean 
-  * *Apply the second contact mask and etch staircase contacts* 
-  * Strip PR and wafer clean 
-  * *Repeating staircase contact litho, etch and clean* 
-  * Remove hard mask and wafer clean 
-  * TiN liner deposition 
-  * W deposition 
-  * W CMP 
-  * Wafer clean 
-  * Oxide CVD 
-  * V1 mask 
-  * V1 etch, PR strip, and clean 
-  * Oxide CVD 
-  * M1 mask 
-  * M1 etch, PR strip, and clean 
-  * TiN deposition, W CVD and W CMP 
-  * Oxide CVD 
-  * V2 mask 
-  * V2 etch, PR strip, and clean 
-  * TiN deposition, W CVD, W CMP 
-  * Oxide CVD 
-  * M2 mask 
-  * M2 etch, PR strip, and clean 
-  * TaN deposition, Cu seed deposition, Cu plating, Cu anneal and Cu CMP 
-  * Oxide CVD 
-  * V3 mask 
-  * V3 etch, PR strip, and clean 
-  * TiN deposition, W CVD, W CMP 
-  * PVD TiN, PVD Al-Cu and PVD TiN 
-  * M3 mask 
-  * M3 etch TiN/W/TiN metal stack, PR strip and clean 
-  * Oxide CVD and nitride CVD 
-  * Bond pad mask 
-  * Etch nitride/oxide 
-  * PR strip and clean 
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- 
-### Sources 
-  * Xiao, H. (2016). 3D IC Devices, Technologies, and Manufacturing. SPIE press. 
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