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fab-process-flow.md [2026/05/13 16:49] – [Sources] gauthier.roussilhe.extfab-process-flow.md [2026/05/13 16:53] (current) – [Sources] gauthier.roussilhe.ext
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 New advanced nodes (logic and memory) put an additional strain on fab production. According to SEMI : "since 2020, fab cycle times have grown at a compound annual growth rate of 14.8%. This represents a fundamental deceleration in fab throughput, meaning that even with the same number of tools and consistent utilization rates, the volume of wafers that can be processed is now structurally constrained." They point this growth to "rising process complexity, increased equipment density, and tighter quality control requirements" (equipment spending per wafer area has surged over 150% since 2020). In the case of advanced memory, SEMI notes that "HBM wafers consume over three times more wafer area per bit compared to standard DRAM, creating potentially significant wafer demand." New advanced nodes (logic and memory) put an additional strain on fab production. According to SEMI : "since 2020, fab cycle times have grown at a compound annual growth rate of 14.8%. This represents a fundamental deceleration in fab throughput, meaning that even with the same number of tools and consistent utilization rates, the volume of wafers that can be processed is now structurally constrained." They point this growth to "rising process complexity, increased equipment density, and tighter quality control requirements" (equipment spending per wafer area has surged over 150% since 2020). In the case of advanced memory, SEMI notes that "HBM wafers consume over three times more wafer area per bit compared to standard DRAM, creating potentially significant wafer demand."
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 ### Sources ### Sources
  
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   * Lapedus, M. (2017). [Battling Fab Cycle Times](https://semiengineering.com/battling-fab-cycle-times/), Semiconductor Engineering.   * Lapedus, M. (2017). [Battling Fab Cycle Times](https://semiengineering.com/battling-fab-cycle-times/), Semiconductor Engineering.
   * Yoon, S. (2025). [From Latency to Reaction: Simulating the Next Wafer Demand Inflection](https://www.semi.org/en/blogs/from-latency-to-reaction-simulating-the-next-wafer-demand-inflection), SEMI.   * Yoon, S. (2025). [From Latency to Reaction: Simulating the Next Wafer Demand Inflection](https://www.semi.org/en/blogs/from-latency-to-reaction-simulating-the-next-wafer-demand-inflection), SEMI.
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 ## Yield modelling ## Yield modelling
  
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 The figure below from May & Spanos summarized the different yield calculation steps. The figure below from May & Spanos summarized the different yield calculation steps.
  
-![Manufacturing process flow from the perspective of yield monitoring and control. May & Spanos](/yield-modelling.png)+{{:yield-modelling.png?800|Manufacturing process flow from the perspective of yield monitoring and control. May & Spanos}} 
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 ### Sources ### Sources
   * May, G. S., & Spanos, C. J. (2006). Fundamentals of semiconductor manufacturing and process control. John Wiley & Sons.   * May, G. S., & Spanos, C. J. (2006). Fundamentals of semiconductor manufacturing and process control. John Wiley & Sons.
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 ## Front-end process flow ## Front-end process flow
  
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 The process flow can be summarized in different ways. From a fab operations perspective, Mönch et al provide a simple view of the looping dynamics on front-end processes. The process flow can be summarized in different ways. From a fab operations perspective, Mönch et al provide a simple view of the looping dynamics on front-end processes.
  
-![Operations in a wafer fab. Mönch et al](/wafer-fab-flow.png)+{{:wafer-fab-flow.png?800|Operations in a wafer fab. Mönch et al}}
  
 May and Spanos propose a simplified process flow for a planar CMOS, a simpler flow compared to today's 3D structures. May and Spanos propose a simplified process flow for a planar CMOS, a simpler flow compared to today's 3D structures.
  
-![Operations in a wafer fab. Mönch et al](/cmos-process-flow.png)+{{:cmos-process-flow.png?800|}} 
  
 Going deeper, Plummer et al decompose all the sub-steps that go into a photoresist deposition step for an old manufacturing process. On a more technical view, Franssila shows what happens in an epitaxy reactor, including sub-steps timing and temperature variation. Going deeper, Plummer et al decompose all the sub-steps that go into a photoresist deposition step for an old manufacturing process. On a more technical view, Franssila shows what happens in an epitaxy reactor, including sub-steps timing and temperature variation.
  
-{{:wafer-fig-03.jpg?400|Left: typical photoresist process flow for DNQ g-line and i-line positive resists. Plummer et al. Right: single wafer epitaxy reactor running SiHCl3 process. Franssila}}+{{:wafer-fig-03.jpg?800|Left: typical photoresist process flow for DNQ g-line and i-line positive resists. Plummer et al. Right: single wafer epitaxy reactor running SiHCl3 process. Franssila}}
  
 On more recent technology nodes, Jung shows the different steps depending of patterning techniques for logic and DRAM devices. The looping sequences are particulary visible here and shows the complexity depending of selected processes. On more recent technology nodes, Jung shows the different steps depending of patterning techniques for logic and DRAM devices. The looping sequences are particulary visible here and shows the complexity depending of selected processes.
  
-![Operations in a wafer fab. Mönch et al](/patterning.png)+{{:patterning.png?800|}}
  
 More comprehensive process flows have been explored for [[dram-case.md|3D devices on RAM]] and [[3dnand-case.md|3D NAND Flash]]. More comprehensive process flows have been explored for [[dram-case.md|3D devices on RAM]] and [[3dnand-case.md|3D NAND Flash]].