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fab-process-flow.md [2026/05/13 16:51] – [Sources] gauthier.roussilhe.extfab-process-flow.md [2026/05/13 16:53] (current) – [Sources] gauthier.roussilhe.ext
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 ### Sources ### Sources
   * May, G. S., & Spanos, C. J. (2006). Fundamentals of semiconductor manufacturing and process control. John Wiley & Sons.   * May, G. S., & Spanos, C. J. (2006). Fundamentals of semiconductor manufacturing and process control. John Wiley & Sons.
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 ## Front-end process flow ## Front-end process flow
  
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 The process flow can be summarized in different ways. From a fab operations perspective, Mönch et al provide a simple view of the looping dynamics on front-end processes. The process flow can be summarized in different ways. From a fab operations perspective, Mönch et al provide a simple view of the looping dynamics on front-end processes.
  
-![Operations in a wafer fab. Mönch et al](/wafer-fab-flow.png)+{{:wafer-fab-flow.png?800|Operations in a wafer fab. Mönch et al}}
  
 May and Spanos propose a simplified process flow for a planar CMOS, a simpler flow compared to today's 3D structures. May and Spanos propose a simplified process flow for a planar CMOS, a simpler flow compared to today's 3D structures.
  
-![Operations in a wafer fab. Mönch et al](/cmos-process-flow.png)+{{:cmos-process-flow.png?800|}} 
  
 Going deeper, Plummer et al decompose all the sub-steps that go into a photoresist deposition step for an old manufacturing process. On a more technical view, Franssila shows what happens in an epitaxy reactor, including sub-steps timing and temperature variation. Going deeper, Plummer et al decompose all the sub-steps that go into a photoresist deposition step for an old manufacturing process. On a more technical view, Franssila shows what happens in an epitaxy reactor, including sub-steps timing and temperature variation.
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 On more recent technology nodes, Jung shows the different steps depending of patterning techniques for logic and DRAM devices. The looping sequences are particulary visible here and shows the complexity depending of selected processes. On more recent technology nodes, Jung shows the different steps depending of patterning techniques for logic and DRAM devices. The looping sequences are particulary visible here and shows the complexity depending of selected processes.
  
-![Operations in a wafer fab. Mönch et al](/patterning.png)+{{:patterning.png?800|}}
  
 More comprehensive process flows have been explored for [[dram-case.md|3D devices on RAM]] and [[3dnand-case.md|3D NAND Flash]]. More comprehensive process flows have been explored for [[dram-case.md|3D devices on RAM]] and [[3dnand-case.md|3D NAND Flash]].