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--- front-end.md [2026/03/24 16:09] – gauthier.roussilhe.ext
+++ front-end.md [2026/03/24 16:16] (current) – [Supporting images] gauthier.roussilhe.ext
@@ Line 86: / Line 86: @@
   * 30% of all front-end processing steps are cleaning steps on average
   * Advanced nodes need more cleaning (more layers for advanced memory for instance)
 ### Supporting images
-[System configuration for Screen WS series](https://hdjp-corporateweb-files-spe.screen.co.jp/6617/1464/0785/product_system.png)
-  * Legend: QDR: Quick Dump Rising bath ; FR: Final Rinsing bath ; SD: Spin dryer ; EDR: Dump Rinsing bath
   * [Partial process video from AP&S](https://www.ap-s.de/wp-content/uploads/2022/12/APS-Demo-Center-1.mp4)
+{{:product_system.png?800|}}
+Legend: QDR: Quick Dump Rising bath ; FR: Final Rinsing bath ; SD: Spin dryer ; EDR: Dump Rinsing bath
@@ Line 458: / Line 459: @@
   * A CMOS integrated circuit with embedded memory may require more than 60 implant steps (Applied Materials).
   * A large wafer fabricator may process up to 50,000 wafers/month, with each wafer requiring 20 to 30 implants. This output requires the use of about 20 implanters, each with the capacity to implant more than 200 wafers/h (Axcelis).[Link](https://www.axcelis.com/wp-content/uploads/2019/02/Ion_Implantation_in_Silicon_Technology.pdf)
 ### Supporting images
-  * Dose and energy requirements of major implantation applications (species shown roughly in
-order of decreasing usage) (Fig2 here: https://www.axcelis.com/wp-content/uploads/2019/02/Ion_Implantation_in_Silicon_Technology.pdf)
   * [Axcelis Purion H6   * High Current Ion Implanter](https://www.youtube.com/watch?v=K-qvAKKLQVM)
+{{:screenshot_2026-03-24_at_16.11.02.png?800|}}
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 #### 8.3. Electrochemical Deposition (ECD) / Plating
   * To be defined
 ### Manufacturers
   * [Applied Materials](https://www.appliedmaterials.com/eu/en/product-library.html)
@@ Line 531: / Line 530: @@
   * [ASM International](https://www.asm.com/)
   * [TEL](https://www.tel.com/)
 ### Equipments
   * LAM [Altus Family](https://www.lamresearch.com/product/altus-product-family/):  CVD (W) and ALD (WN, Mo) processes/ Advanced memory and logic: 3D NAND, DRAM, Interconnect, WN Barrier (via and metallizatio)
@@ Line 570: / Line 568: @@
 ### Supporting images
-  * [Multiple processes required to enable Co conductors](https://www.appliedmaterials.com/content/dam/appliedmaterialsincprogram/2_Process_Sequence.png)
+{{:2_process_sequence.jpg?800|}}
 ### Sources
@@ Line 609: / Line 608: @@
 ### Misc
   * [Ebara catalog](https://www.ebara.com/content/dam/ebara/grand-masters/entities/en/products/precision-pump/pdf/80002E_26_20.pdf)
-  * Chemical Mechanical Planarization, [CMP Process Fundamentals: Sec 2   * CMP Tools and Process](https://www.youtube.com/watch?v=2z4lq-Ms_OU) ; [CMP Process Fundamentals: Sec 3   * CMP Slurries](https://www.youtube.com/watch?v=lWvvKGkFDfk)
+  * Chemical Mechanical Planarization, [CMP Process Fundamentals: CMP Tools and Process](https://www.youtube.com/watch?v=2z4lq-Ms_OU) ; [CMP Process Fundamentals: CMP Slurries](https://www.youtube.com/watch?v=lWvvKGkFDfk)
 ### Sources