The preliminary cleaning step is primordial to kickstart the other cleaning processes. The purpose is to remove large impurities that might be present on the pre-processed wafer. ¹⁾

• Sulfuric acid (H2SO4)
• Hydrogen peroxide (H2O2)
• Hydrofluoric acid (HFA)
• Deionized water (DI Water)

• Sulfur residues
• Gross impurities

The oxidation reaction removes sulfur residues ²⁾ $$ S_x + 2H_2SO_4→ 3SO_2 + 3H_2O $$

For the HF reaction ³⁾ $$ SiO_2​+6HF→H_2​SiF_6​+2H_2​O $$

The purpose of this initial cleaning step is to remove organic contaminants, such as silicon films and trace metals, from the surface of the wafer. ⁴⁾ This involves submerging the silicon wafer in two consecutive cleaning solutions: SC-1 and SC-2. Complexing refers to the process whereby a positively charged metallic ion shares electrons with the NH₄OH molecule. This is followed by oxidative desorption, a first-order reaction that oxidises the product to be removed, which can then be flushed out by reacting with a strong acid (HF). The result is a water-soluble solution.

The ratio used for the SC-1 solution is as follows: a range of 5:1:1 to 7:2:1 of H₂O, H₂O₂ and NH₄OH, respectively. ⁵⁾

• Hydrogen peroxide (H2O2)
• Ammonium hydroxide (NH4OH)
• Deionized water (DI Water)

• SiO2 (thin film) ⁶⁾
• Dissolved organics contaminants originally synthetic waxes, resins and oils due to grease. Also composed of organic solvents residues and photoresist. ^{7) 8)}
• Complexed metal ions (Fe, Ni, Cu & Na) ⁹⁾
• Metals (Gold, silver and copper) ¹⁰⁾

Metalic Ion (charged positively) : $$ Cu²⁺ + 4 NH₄OH → [Cu(NH₃)₄]²⁺ + 4 H₂O $$

Desorption reaction: Thermal desorption of gasses ¹¹⁾ Organic components react with the peroxyde in change produces CO2, water and heat.

$$ CₓHᵧ + H₂O₂ → CO₂ + H₂O $$

Overall, the SC-1 step is a slightly exothermic reaction that produces heat. The ideal operating conditions are a temperature range of between 70 and 80 degrees Celsius. As the reaction also presents low thermal stability, temperature control is essential. Immersion time is also an important variable for this step.

The key objective of this cleaning step is to remove alkalyne residues, trace metals and hydroxyde metals. ¹²⁾

The composition of the SC-2 solution is as follows: a ratio of H₂O, H₂O₂, HCl by volume ranging from 6:1:1 to 8:2:1. ¹³⁾

• Hydrochloric acid (HCl)
• Hydrogen peroxide (H2O2)
• Deionized water (DI Water)

• Trace metals (Au, Ag) ¹⁴⁾
• Metal hydroxides (Al(OH)3, Fe(OH)3, Mg(OH)2 & Zn(OH)2) ¹⁵⁾

$$ M_x + 2HCL→ M_xCL_2 + 2H^+ $$

The reactions occurring during these steps are more stable; therefore, the temperature and immersion time in the bath do not need to be controlled as strictly. The solution temperature must be within the range of 70 degrees Celsius +/- 5, with a bath time of approximately 10 minutes.

The aim of this final step is to remove the residues of oxidation that were produced in the previous reactions.

• Hydrofluoric acid (HF)

• Silicon oxides ¹⁶⁾
• Other type of oxides

$$ SiO_2 + 4 HF → SiF_4 + H_2O $$

This step involves immersing the wafer in a hydrofluoric acid solution and then rinsing it with deionised water. This makes the oxides soluble. The immersion takes around 15 seconds. It's a cleaning step that can be used multiple times in a cleaning procedure, as it is highly effective at removing silicon oxides formed during etching processes.

This reaction works in the same way as the SC-1 to clean photoresist specifically. Piranha eats away at the photoresist mask and any heavy organic components present on the wafers.

• Sulfuric acid (H2SO4)
• Hydrogen peroxide (H2O2)
• Deionized water (DI Water)

• SiOH (thin film) ¹⁷⁾

$$ H₂SO₄ + H₂O₂ → H₂SO₅ + H₂O $$

This creates the possibility of producing peroxymonosulfuric acid, which reacts with the organic components of the photoresist film. $$ CₓHᵧ + H₂SO₅ → CO₂ + H₂O + SO₄²⁻ $$

This process seems similar to SC_1; the operating temperatures vary greatly depending on the stability of the reaction. It also appears to be the initial preliminary step applied to wafers, as it uses a mixture of highly reactive acids towards organic components. This means it is used to clean off the larger imperfections attached to the wafers beforehand.¹⁸⁾

This is another step whose goal is to clean the organic components present on the wafer after RCA cleaning. This is done through baths or spray processes, which cover the wafer in highly concentrated ozone solutions.

The solution consists of these components at an O₃ concentration varying between 10 and 15 ppm.

• Ozone (O3)
• Deionized water (DI Water)

• CO2
• H2O

$$ –(CH₂)ₙ– + 3n O₃ → n CO₂ + n H₂O $$

This step illustrates the various ways in which peroxide solutions can be used to clean silicon wafers. APM refers to ammonia peroxide mixtures. BPM stands for basic peroxide mixtures. HPM stands for hydrochloric peroxide mixtures. These steps are mostly related to RCA procedures. The same chemical principles underpin them all, with different mixtures of H₂O₂ being used to remove organic residues. While these steps may resemble the RCA SC procedures, they do not react with trace metals through oxidative desorption.

• Ammonium peroxide / buffered peroxide / hydrochloric peroxide mixtures (Containing H2O2)
• Sulfuric acid (H2SO4)
• Different concentration are used depending on the solutions used (solutions of 98% wt H2SO4 and 30% wt H2O2 often used, wth ratios of 2:1 - 4:1 respectively).

• Organic residues
• Water
• CO2

$$ CₓHᵧ + H₂O₂ → CO₂ + H₂O $$

Some of the reactions associated with different concentrations of H₂O₂ vary in terms of operating conditions. For example, if you look at a solution with the same concentration of H2O2 as the SC-1, the temperature must range from 70 to 75 degrees Celsius. However, with alternative dilution and concentration ratios, the operating temperature can range from 100 to 130 degrees Celsius, with immersion times of 10 to 15 minutes.

Plasma cleaning is one of the dry cleaning methods. When plasma is mentioned in the literature, it can refer to multiple processing steps, such as bulk photoresist removal, etching, predeposition cleaning, and surface conditioning. In processing cleaning, this step only involves removing bulk photoresist material after etching and ion implantation. The intake of 10% H₂ and 90% N₂ (specifically for O₂ plasma) creates a non-oxidising environment when used to feed the devices. They also act as plasma cleaning gases.

• O2 plasma (most common) / Ar plasma / H2 plasma
• H2
• N2

• CO2
• H2O
• CO (volatile components)

$$ CₓHᵧ + O* → CO₂ + H₂O $$

Plasma cleaning is performed at low pressure, depending on the gas used and the specific technique employed. There are multiple techniques, each with a different purpose. Ar and H₂ bombardment, for example, are used to clean native oxides and thin contamination layers.

This cleaning step involves exposing the surface to UV light of a specific wavelength. This light reacts with certain organic molecules and ambient oxygen to create ozone (O₃). The resulting ozone has a strong oxidising potential, enabling it to react with the dissociated molecules that are by-products of the UV reaction. As the reaction continues, the O₃ is also destroyed by absorption.

• Ozone (O3)
• UV light

• H2O
• CO2
• N2
• VOC (Volatile Organic Compounds)

This is the global formula for ozone cleaning. $$ Cx​Hy​+O∙(1D)/O3​→CO2​+H2​O $$

Where $$ O∙(1D)/O3 $$ The generation of ozone is caused by the reaction of O2 with UV.

This is usually done at 120°C and 500 Torr.

It is also a dry-cleaning method.

• Carbon dioxide (CO2)
• Argon (Ar)
• Nitrogen (N2)

• Submicron particles
• Trace organic residues

This is done through the spraying effect of a mixture of cryogenic gases.

It includes the Ohmi Clean process.

• Acoustic waves
• NH4OH / H2O2 (very dilluted) (0,1 to 1% v/v)
• Deionized water (DI Water)

• Contaminated DI
• Sub 100nm particles

• PVA brush (polyvinyl alcohol)
• NH4OH (0,1% wt)
• HF
• Deionized water (DI Water)

• CMP slurry
• Gross particles (diameter greater than 21 um)

• Electrochemical clean

• LAM Research
• TEL
• Applied Materials
• Screen
• PSK
• Others (Rena, AP&S, etc.)

• LAM DV-Prime & Da Vinci Product Families: wet clean, spin / Photoresist removal ; particle, polymer, and residue removal ; silicon substrate thinning/stress relief
• LAM EOS Product Families: wet clean / FinFET ; Particle, polymer, and residue removal
• TEL Expedius: pre-diffusion/oxidation clean, post-etch clean, resist stripping, wet etch of Oxide/Nitride for 3D NAND device / 300mm
• TEL Cellesta: Pre/Post clean, Wet etch, dry process (New IPA dry /SMD/Spin dry) / 300mm
• TEL NS Series: D.I. Water brush clean, N2, brush / 150 to 300mm
• TEL Antares: dry clean with cryogenic aerosol / 300mm (works for metal and low-k films)
• TEL ZETA: Post etch clean, RCA clean, DHF wet etch (for photoresist stripping)
• Screen [FC-3100]https://www.screen.co.jp/spe/en/products/fc-3100): Wet clean / 300mm
• Screen WS-620C/WS-820C/WS-820L: Wet clean / 150 to 200mm
• Screen FC-821L: Wet clean / 200mm
• Screen CW-2000: Wet clean (including RCA clean) / 50 to 200mm
• Screen SU-3400: Spin processor / 300mm
• Screen SU-3300S: Spin scrubber / 300mm

• 30% of all front-end processing steps are cleaning steps on average
• Advanced nodes need more cleaning (more layers for advanced memory for instance)

• Partial process video from AP&S

Legend: QDR: Quick Dump Rising bath ; FR: Final Rinsing bath ; SD: Spin dryer ; EDR: Dump Rinsing bath

• Reinhardt, K., & Kern, W. (Eds.). (2018). Handbook of silicon wafer cleaning technology. William Andrew. MAIN SOURCE
• Rużyłło, J. (Ed.). (1998). Proceedings of the fifth international symposium on cleaning technology in semiconductor device manufacturing. The Electrochemical Society.
• Bera, B. (2019). Silicon Wafer Cleaning: A Fundamental and Critical Step in Semiconductor Fabrication Process. International Journal of Applied Nanotechnology, 5(1), 8-13.
• Microtech Systems, RCA Critical Cleaning Process
• Allan Chemical Corporation, Checklist for RCA Cleaning Process Chemicals
• Modutek Corporation, Wafer Cleaning Process

This processing step has the goal of creating a layer of silicon dioxide (SiO2), contrary to the cleaning step, this thin layer of silicon dioxide serves as a growth step, it acts as the dielectric component of the wafer. ^{19) 20)}. This process can be achieved with two distinct methods. n

Process in which the wafer is exposed to high temperature water vapor. The oxidation occuring creates a film that will act as the gate dielectric agent. ^{21) 22)}

• Water (H2O) vapor
• Oxygen (O2)

• Silicon dioxide (SiO2)
• Hydrogen (H2)

$$ Si+2H_2O →SiO_2+2H_2 $$

This film is thicker and presents less uniformity than the one created through a dry oxidation process. The offset is that the growth rate present on the silicon wafer is faster when using this method. The temperature of operation is between 800 - 1000° Celsius.

This method exposes the wafer to an environment consisting of only Oxygen. The oxidation occurs more slowly then with the wet processing, but produces a more uniform and denser silicon dioxide layer. ²³⁾

• Oxygen (O2)
• Nitrogen (N2)

• Silicon dioxide (SiO2)

$$ Si+O_2 →SiO_2 $$

Process temperature varies between 900 - 1000 Celsius.

• Kokusai
• Applied Materials
• ASM
• TEL

• Kokusai AdvancedAce-II: Oxidation ; CVD ; film deposition
• Kokusai AdvancedAce-300: Oxidation ; LP CVD ; Diffusion ; Annealing
• Kokusai Vertron Revolution: Oxidation ; CVD ; film deposition
• Kokusai Quixace-II: Oxidation ; CVD ; film deposition
• TEL Telindy Series: Oxidation, annealing, LPCVD / 300mm
• See Deposition for more references

• Centura Xtera EPI process

• Gronet, C. M., Knoot, P. A., Miner, G. E., Xing, G., Lopes, D. R., & Kuppurao, S. (2000, March 14). Method and apparatus for insitu vapor generation (U.S. Patent No. 6,037,273). U.S. Patent and Trademark Office. https://patents.google.com/patent/US6037273
• Homma, K., & Yomiya, K. (1998, July 7). Processing furnace for oxidizing objects (U.S. Patent No. 5,777,300). U.S. Patent and Trademark Office. https://patents.google.com/patent/US5777300A/en
• Yokota, Y., Ramamurthy, S., Achutharaman, V., Czarnik, C., Behdjat, M., & Olsen, C. (2006, October 5). Thermal oxidation of silicon using ozone (U.S. Patent Application Publication No. US 2006/0223315 A1). U.S. Patent and Trademark Office. https://patents.google.com/patent/US20060223315A1/en
• Fukada, T., Yoo, W. S., Hiraga, Y., Kang, K., & Komatsubara, R. (2001, September). Wet oxidation using single wafer furnace. In 9th International Conference on Advanced Thermal Processing of Semiconductors, RTP 2001 (p. 120). IEEE.

This process consists of adding thin film to the wafer, who's role will either to act as a structural layer or a spacer to be etched. These process are physicochemical processes. ²⁴⁾

Various precursor gases are sent to the reactor (vacuum chamber) whose's atmosphere consists of pure inert gases. The reaction occurs with the surface of the wafer thanks to the action of the plasma generated with a certain electrical field. The plasma forms radical that in turn react and form a coating on the wafer.

• Silane (SiH4)
• TMS
• C4F8
• N2O
• NH3
• N2
• Ar
• H2

• SiO2 / Si3N4
• HCl
• HF
• H2

Various chemical reactions occur depending of the precursors. ^{25) 26)}

$$ SiH_4+NH_3→Si_3N_4 + H_2 $$ $$ SiH_4+N_2O→SiO_2+ N_2 + H_2 $$ $$ SiH_4+ CH_4 → SiC + H_2 $$

Pretty low temperature, can vary from room temperature to 400 Celsius.

This deposition method relies on a metallic precursor reacting with the surface thanks to the presence of plasma. Every cycle also includes a purge that removes the excess reactants and by-products. These cycles are composed of an Half cycle A where the precursor is deposited on the surface. The second cycle is where the plasma reacts with the said precursor to form the film. The presence of plasma also eliminates the presence of excess reactants and by products on the surface.

• TMA (AL(CH3)3) ²⁷⁾
• Oxygen plasma (O2)

• Alumina (Al2O3)
• CH4
• CO2
• H2O ²⁸⁾

Half cycle A, deposition on the surface $$ –OH* (surface) + Al(CH₃)₃ → –O–Al(CH₃)₂* + CH₄ $$ Half cycle B, reaction of precursor with the plasma $$ –Al(CH₃)ₓ* + O* (plasma) → –Al–OH* + CO₂ + H₂O $$

These reactions can be done at lower operating temperature due to the presence of plasma in the reaction.

Plasma cleaning is often used after the thin film deposition processes to clean out the chamber in which the reactions took place. Plasma reacts with the oxides and film remaining on the walls. ²⁹⁾

• Nitrogen triflurore (NF3)
• C2F6
• Ar
• N2

• Volatile fluorure compunds
• O2
• N2

Plasma formation : $$ NF₃ → NFₓ + F* $$ Reaction with the film $$ SiO₂ + 4F* → SiF₄ + O₂ $$ $$ > Si₃N₄ + 12F* → 3SiF₄ + 2N₂ $$

• Kokusai
• Applied Materials
• TEL

• Kokusai Tsuguri: Thin film deposition
• Kokusai Tsuguri-C2: Thin film deposition
• Kokusai Quixace-LV: Thin film deposition
• Applied Materials Centura Prime EPI: epitaxial growth
• Applied Materials Centura Xtera EPI: epitaxial growth / advanced logic (GAA, FinFET) and memory (3D)
• See Deposition for more references

• Hollister, A., Reddy, S., Fox, K., Sriram, M., & Womack, J. (2015, August 25). PECVD deposition of smooth silicon films (U.S. Patent No. 9,117,668). U.S. Patent and Trademark Office. https://patents.google.com/patent/US9117668B2/en
• Kintek, What gases are used in PECVD? Master the Chemistry for Superior Thin Films
• Lavoie, A., Saly, M. J., Moser, D., Odedra, R., & Kanjolia, R. (2013, August 15). Precursors for plasma activated conformal film deposition (U.S. Patent Application Publication No. US 2013/0210241 A1). U.S. Patent and Trademark Office. https://patents.google.com/patent/US20130210241A1/en
• NCCAVS Plasma Applications Group (PAG) Users Group. (2017, September 13). Advances in atomic layer deposition (ALD): PAG users group meeting agenda [Conference agenda]. Northern California Chapter of the American Vacuum Society.
• Sigma-Aldrich. (n.d.). Silicon nitride by atomic layer deposition [Technical article]. MilliporeSigma.

g

The aim of these processes is to create a photoresistive layer. This layer will subsequently be exposed using either deep ultraviolet (DUV) or extreme ultraviolet (EUV) light. The photoresist is formed using a resin.

This process uses two types of laser: either a KrF laser with a wavelength of 248 nm, or an ArF laser with a wavelength of 193 nm.

• Peroxo-polyacids of tungsten ³⁰⁾
• Tungsten
• Niobium
• Titanium
• Tantalum
• Polymer binder for Chemically Amplified Resist (CAR)
• 248nm CAR option: Poly-hydroxystyrene (PHOST)
• 193nm CAR option: Acrylate / methaacrylate polymers
• tBOC groups: tert-butyl ester, tert-butoxycarbonyl
• Cyclohexanone (solvents)³¹⁾
• TMAH solution (Tetramethylammonium Hydroxyde): Photoacid generator (PAG) ³²⁾, Triarylsulfonium salts, Diaryliodonium salts, Sulfonates
• Base additive³³⁾: Triisobutylamine, Triisooctylamine, Diethanolamine, Triethanolamine

• Solvent vapor (cyclohexanone) ³⁴⁾
• TMAH solution

• Metal-oxide resist: Tin-oxide (SnO2), Hafnium oxide (HfO2), Zirconium oxide (ZrO2), Zinc oxide (ZnO) ^{35) 36) 37)}
• Chemically Amplified Resist (CAR): Polymer³⁸⁾, tert-Butyl methacrylate (t-BMA)
• Photoacid Generator (PAG): Sulfonium Salts (tryphenylsulfonium Triflate), Iodium salts
• Quencher ³⁹⁾: Tetrabutylammonium hydroxide (TBAH), Triethylamine (TEA), Triisobutylamine / Triisooctylamine
• Solvents: n-hexane, Toluene, Chloroform, Propylene Glycol Methyl Ether Acetate (PGMEA), Butyl acetate, Ethanol, Methanol

• Benzene ⁴⁰⁾
• Tert-butanol
• Diphenyl sulfide
• PGMEA

Hexamethyldisilazane surface functionalization

$$ Si–OH + (CH₃)₃Si–NH–Si(CH₃)₃ → Si–O–Si(CH₃)₃ + NH₃ $$

This reaction makes the surface hydrophobic.

• Soft bake, evaporation of solvent
• EUV exposition
• Post exposure bake (PEB)

$$ Polymer–O–C(CH₃)₃ + H⁺ → Polymer–OH + C₄H₈ (isobutylene) + H⁺ $$

• TEL
• Fujifilm
• JSR
• Shin Etsu Chemical

• TEL Clean Track Act 12: DUV / 200 to 300mm
• TEL Lithius Series: i-line, KrF, ArF, ArFi, EUV / 200 to 300mm
• See Deposition for more references

• Material used for negative photoresist: aromatic xylene
• Material used for positive photoresist: ethyl ethoxyacetate
• Look into resist process tools (“tracks”)

• Woo, C., Kang, E., Kim, J., Kim, J., Kim, T., Namgung, R., Moon, K., Cheon, H., Chae, S., & Han, S. (2021, October 7). Semiconductor photoresist composition and method of forming patterns using the composition (U.S. Patent Application Publication No. US 2021/0311387 A1). U.S. Patent and Trademark Office. https://patents.google.com/patent/US20210311387A1/en
• Wang, X., Tao, P., Wang, Q., Zhao, R., Liu, T., Hu, Y., … & He, X. (2023). Trends in photoresist materials for extreme ultraviolet lithography: A review. Materials Today, 67, 299-319.
• Hasan, M. W., Deeb, L., Kumaniaev, S., Wei, C., & Wang, K. (2024). Recent advances in metal-oxide-based photoresists for EUV lithography. Micromachines, 15(9), 1122.
• MicroChemicals GmbH. (n.d.). Spin-coating [Application note].

Photolithography processing is a crucial step in which a pattern from a mask is applied to a substrate surface. In this case, the substrate is a wafer. Photolithography relies on the interaction between a photoresist polymer layered on the substrate and a specific wavelength of light. Patterns are drawn onto the wafer through this interaction, and by repeating this step, wafers with multiple layers can be built. Below is a list of the main stages of the photolithography process, which are repeated in the order presented (note: all these processes are shared by the different photolithography methods). ⁴¹⁾⁴²⁾:
Substrate preparation: The substrate's surface must be cleaned and prepared for good adhesion of the photoresist. Traditionally, this is done by cleaning the wafer surface with the cleaning processes in section 1, performing a dehydration bake to remove the water adsorbed by the substrate, and finally applying an adhesion promoter. The dehydration bake is usually performed at temperatures ranging from 200 to 400°C for 30 to 60 minutes in a dry environment. The adhesion promoter is then immediately applied to the dry surface. These promoters are typically silanes, most notably hexamethyl disilazane (HMDS), which react with the silanol groups on the wafer surface to improve photoresist adhesion.

Photoresist coating (see above): This step involves applying the photoresist to the surface of the wafer, typically using a spin or spray coating method. Before coating, the photoresist material is liquefied by mixing it with a solvent. The difference lies in how the spinning action is performed. Either the wafer is spun with the photoresist solution applied to its surface, or the wafer remains stationary while the solution is coated dynamically. The important parameters of these steps are the uniformity and thickness of the resulting coating.

Post-apply bake (also soft bake): This baking step occurs directly after the photoresist coating. The objective is to remove excess solvent from the photoresist surface. This is traditionally done by baking in a convection oven at 90°C for 30 minutes. Removing the excess solvent increases the stability of the photoresist coating.

Alignement and exposure: In short, this step involves projecting light through a photomask to draw patterns onto a photoresist-coated substrate. The wavelength of the light depends on the technique used: 248 nm or 193 nm for deep ultraviolet, and 13.5 nm for extreme ultraviolet. Between each exposure step, the mask must be aligned with the last pattern drawn on the wafer to maximise the packing capacity of the wafer. An important side effect of this step is the standing wave effect, which occurs when ultraviolet light is reflected off the wafer's surface. This causes ridges to be imprinted between every layer of resist on the wafer.

Post-exposure bake: The objective of this step is to reduce the standing wave effect resulting from the previous processing step. This is achieved by applying a bake to the processed wafer. The heat reacts with the chemically amplified resist, resulting in smoother edges.

Development: In the development step, a developer — typically an aqueous solution containing tetramethylammonium hydroxide (TMAH) — is applied to the surface of the photoresist to control its profile. This is achieved using a variety of application methods, such as spraying and puddling.

Post-bake: This step involves the final heat treatment, which hardens the wafer surface in preparation for the harsh conditions of subsequent processing steps. This baking is carried out at temperatures ranging from 120 to 150 degrees Celsius.

This type of photolithography uses krypton fluoride (KrF) lasers to produce deep ultraviolet light at a wavelength of 248 nm. This light is generated by electrical discharges sent through a chamber containing krypton, fluoride and neon. The optimal pressure conditions for the gas mixture in the chamber are between 2.6 and 3.1 atm. ⁴³⁾ The F2:Kr:Ne gas mixture is 3:70:2600 mbar. This method enables a high power output of 300 W and a reflection coefficient of 99%. Neon acts as the buffer and carrier gas. Between operations, the chamber is purged with pure N₂ to minimise interaction with accumulated air or water. The purge gases are filtered as they are output and recirculated.

• Krypton (Kr)
• Fluor (F2)
• Neon (Ne)
• Calcium fluoride (CaF2) (mixing plate)
• Nitrogen (N2)

The reaction that occurs in the chamber goes as follows ⁴⁴⁾ : $$ Kr + F₂ + Ne_ → KrF_ → KrF + hν (248 nm) $$ The resulting nodes of lithography vary from 250 nm to 90 nm.

This photolithography process is the next generation of technological improvement to DUV photolithography. It is based on the same principles as KrF photolithography, but uses a laser that operates with a different mixture of gases. A 193 nm wavelength deep ultraviolet light is produced by an argon fluoride laser. ⁴⁵⁾ The proportions of the gases used are as follows: Helium (94.77%), neon (5%), fluorine (0.23%) and argon (trace amounts). ⁴⁶⁾ The purge gas is also nitrogen.

• Argon (Ar)
• Fluor (F2)
• Neon (Ne)
• Helium (He)
• Calcium fluoride (CaF2) (mixing plate)
• Nitrogen (N2)

The reaction occuring goes as follow : $$ Ar + F₂ + Ne_ → ArF_ → Ar + F + hν (193 nm) $$

The resolution node varies from 65 to 130 nm.

This technique uses the same ArF laser, but a fine layer of ultrapure water is placed between the laser and the wafer surface to improve reflectivity and patterning precision. ⁴⁷⁾ This technique enables nodes to be made much smaller than before, with a resolution of around 20 nm. ⁴⁸⁾ The ultrapure water is constantly recirculated in the chamber.

• Ultra-pure water (UPW)
• Argon (Ar)
• Fluor (F2)
• Neon (Ne)
• Helium (He)
• Calcium fluoride (CaF2) (mixing plate)
• Nitrogren (N2)

This technique relies on the formation of a laser that generates extreme ultraviolet light with a wavelength of 13.5 nm. This laser is induced by the formation of a tin plasma. Droplets of tin are dropped into a chamber and hit by a first CO₂ laser, which causes them to expand. They are then hit by a more powerful CO₂ laser, which transforms them into plasma. This plasma then emits light at a wavelength of 13.5 nm. ⁴⁹⁾ For this to work, the environment must be in a near-vacuum state. ⁵⁰⁾ Hydrogen (H₂) is used for this purpose since it absorbs little EUV light. 600 litres of H₂ are fed into the operating chamber. ⁵¹⁾ In the scanner, the atmospheric gases are a mixture of nitrogen and argon. ⁵²⁾

• Tin droplets (Sn)
• Hydrogen (H2)
• Argon (Ar)
• Carbon dioxide (CO2) laser

• ASML (EUV only provider)
• Nikon
• Canon

• ASML TWINSCAN NXT:2150i: DUV ArFi
• ASML TWINSCAN NXT:21OOi: DUV ArFi
• ASML TWINSCAN NXT:2050i: DUV ArFi
• ASML TWINSCAN NXT:2000i: DUV ArFi
• ASML TWINSCAN NXT:1980Fi: DUV ArFi
• ASML TWINSCAN NXT:1470: DUV ArF
• ASML TWINSCAN XT:1460K: DUV ArF
• ASML TWINSCAN XT:1060K: DUV KrF
• ASML TWINSCAN NXT:870B: DUV KrF
• ASML TWINSCAN NXT:870: DUV KrF
• ASML TWINSCAN XT:860N: DUV KrF
• ASML TWINSCAN XT:860M: DUV KrF
• ASML TWINSCAN XT:400M: i-line
• ASML TWINSCAN XT:260: i-line
• ASML TWINSCAN NXE:3800E: EUV
• ASML TWINSCAN NXE:3600D: EUV
• ASML TWINSCAN NXE:3400C: EUV
• ASML TWINSCAN EXE:5000: EUV High NA
• ASML TWINSCAN EXE:5200B: EUV High NA
• Nikon NSR-S636E: DUV ArFi
• Nikon NSR-S635E: DUV ArFi
• Nikon NSR-S625E: DUV ArFi
• Nikon NSR-S333F: DUV ArF
• Nikon NSR-S322F: DUV ArF
• Nikon NSR-S220D: DUV ArF
• Nikon NSR-SF155: i-line steppers
• Nikon NSR-2205iL1: i-line steppers
• Canon FPA-6300ES6a: KrF
• Canon FPA-6300ESW: KrF
• Canon FPA-3030EX6: KrF
• Canon FPA-5550iZ2: i-line steppers
• Canon FPA-5550iX: i-line steppers
• Canon FPA-3030i6: i-line steppers
• Canon FPA-3030i5a: i-line steppers
• Canon FPA-3030iWa: i-line steppers

• EUV uses Mo/Si mirrors (molybdenum, silicon), 100 layers
• ASML's NXE energy use per wafer pass (NXE:3800E, measured in 2025): 5.5 kWh (2024: 5.9 kWh) Source: ASML Annual Report 2025, p.153

• Ershov, A. I., Partlo, W. N., Brown, D. J. W., & Fomenkov, I. V. (2012). Laser system (U.S. Patent Application No. US 2012/0002687 A1). U.S. Patent and Trademark Office. (Later granted as US 8,908,735 B2).
• Bowering, N. R., Hansson, B. A. M., & Simmons, R. D. (2008). EUV light source (U.S. Patent No. US 7,453,077 B2). U.S. Patent and Trademark Office.
• Bykanov, A. N., Bowering, N., Fomenkov, I. V., Ershov, A. I., & Khodykin, O. (2011). Laser produced plasma EUV light source (U.S. Patent No. US 8,035,092 B2). U.S. Patent and Trademark Office.
• Dinger, U., Eisert, F., Koehler, S., Ochse, A., Zellner, J., Lowisch, M., & Laufer, T. (2007). EUV projection lens with mirrors made from material with differing signs for the rise in temperature dependence of the thermal expansion coefficient around the zero transition temperature (U.S. Patent Application No. US 2007/0035814 A1). U.S. Patent and Trademark Office. (Later granted as US 7,557,902 B2)
• Fomenkov, I. (2017, November 7). EUV source for high volume manufacturing: Performance at 250 W and key technologies for power scaling [Conference presentation]. 2017 EUV Source Workshop, Dublin, Ireland.
• Alagna, P., Rechtsteiner, G., Timoshkov, V., Wong, P., Conley, W., & Baselmans, J. (2016, March). Lower BW and its impact on the patterning performance. In Optical Microlithography XXIX (Vol. 9780, pp. 9-20). SPIE.
• Linde plc. (n.d.). Lithography gases for electronics.
• Nihon Kessho Kogaku Co., Ltd. (n.d.). Product introduction: Optical crystals CaF2.
• Hellma Materials GmbH. (2012). Lithotec calcium fluoride: VUV/DUV/UV, VIS and IR applications [Product datasheet]. Distributed by Sydor Optics.
• Letz, M., Engel, A., Mannstadt, W., Parthier, L., Natura, U., & Knapp, K. (2004, May). CaF2 for DUV lens fabrication: basic material properties and dynamic light-matter interaction. In Optical Microlithography XVII (Vol. 5377, pp. 1797-1804). SPIE.
• Louis, E., Yakshin, A. E., Goerts, P. C., Oestreich, S., Stuik, R., Maas, E. L., … & Ulm, G. (2000, July). Progress in Mo/Si multilayer coating technology for EUVL optics. In Emerging Lithographic Technologies IV (Vol. 3997, pp. 406-411). SPIE.

• Carbon tetrafluoride (CF4)
• Xenon difluoride (XeF2)
• Chlorine (Cl2)
• Fluor (F2)
• Sulfur hexafluoride (SF6)

• Sulfur hexafluoride (SF6)
• Octafluorocyclobutane (C4F8)

• Argon (Ar)

• Chlorine (Cl2)
• Argon (Ar)

• Hydrofluoric acid (HF)
• Potassium hydroxide (KOH)
• Tetramethylammonium hydroxide (TMAH)
• Buffered oxide etchants (BOE)
• Deionized water (DI Water)

• LAM Research
• TEL
• Samco
• ACM Research
• Screen
• PSK
• Applied Materials

• LAM Kiyo Family: Reactive ion etch / Shallow trench isolation, Source/drain engineering, High-k/metal gate, FinFET and tri-gate, Multi-patterning, 3D NAND
• LAM Akara: Plasma-etch / 3D NAND, CFET, 3D RAM
• LAM Coronus: Post-etch for shallow trench isolation, Pre and post deposition, Pre-lithography, Metal film removal, Wet and dry etch bevel protection / 3D NAND
• LAM Flex Product Family: Atomic Layer Etch (ALE), Cryogenic etching, Reactive ion etch (RIE) / Low-k and ultra low-k dual damascene ; Self-aligned contacts ; Capacitor cell ; Mask open ; 3D NAND high aspect ratio hole, trench, contact
• LAM Gamma Product Family: dry strip (photoresist removal) / Advanced memory and logic ; High-dose implant strip (HDIS) ; Bulk strip ; Descum
• LAM Selective Etch Product Family: dry strip (photoresist removal) / Advanced memory (3D NAND, DRAM) and logic (GAA) ; Dummy poly removal ; SiGe removal (GAA) ; Si trimming ; Source/drain deposition preclean ; Low-k material removal ; Surface decontamination and modification
• LAM Sense.i Product Family: Reactive ion etch / Advanced memory (3D NAND, DRAM) and logic ; Conductor etch ; Dielectric etch
• LAM Syndion Product Family: Deep Reactive Ion Etch (DRIE) / Through-silicon vias (TSVs) for high bandwidth memory and advanced packaging
• LAM Vantex Product Family: Cryogenic Etching Reactive Ion Etch (RIE) / 3D NAND high aspect ratio hole, trench, contact ;

Capacitor cell

• Applied Materials Centris Spectral Mo ALD: ALD / Advanced logic (GAA, CFET) and memory (3D)
• Applied Materials Olympia ALD: ALD for dielectric film deposition / Advanced logic (FinFET) and memory (3D)
• Applied Materials Centris Sym3 Y Etch: Unclear / advanced logic and memory
• Applied Materials Centura Etch: RIE and DRIE / 150 to 300mm
• Applied Materials Producer Etch: Unclear
• Applied Materials Producer Selectra Etch: Unclear / advanced logic and memory
• Applied Materials Sym3 Z Magnum Etch: Plasma etch / advanced logic (GAA, CFET) and memory

• Romano, L. (2025). Etching: The art of semiconductor micromachining. Micromachines, 16(2), 213.
• Nojiri, K. (2015). Dry etching technology for semiconductors (pp. 1-116). Cham: Springer International Publishing.
• https://patents.google.com/patent/US20210311387A1/en
• Kanarik, K. J., Tan, S., & Gottscho, R. A. (2018). Atomic layer etching: rethinking the art of etch. The journal of physical chemistry letters, 9(16), 4814-4821.
• O’Hara, A. (2013). Method for etching a sacrificial silicon oxide layer. Japan Patent JP5290172B2.
• Li, Y., Settelmaier, K. T., & Bentner, J. (2009). Anisotropic wet etch device and its production method (China Patent No. CN100524653C). International Business Machines Corporation.
• Chinn, J. D., & Soukane, S. (2005). Etch process for etching microstructures (U.S. Patent No. US6936183B2). Applied Materials, Inc.
• Femto-St (n.d.). Wet etching bench (KOH BHF).

Doping processes are used to introduce conductivity into silicon wafers. These steps are essential for controlling parameters such as junction depth, carrier mobility, leakage current and switch speed. ⁵³⁾

This method of modifying the conductivity of a patterned wafer involves the physical process of directing ions of a specific element towards the wafer's surface, where they act as either n-type or p-type dopers. These ions are conveyed through doping gases, which are carried by inert gases in a chamber. These ions are produced by bombarding the doping gases with electrons, which are typically generated using a hot tungsten rod. ⁵⁴⁾

• Doping gases: Boron trifluoride (BF3), Phosphine (PH3), Arsine (AsH3)
• Carrier gases: Helium (He), Hydrogen (H2), Nitrogen (N2), Argon (Ar)

• Exhaust gases (residual gases)

Here are the electron bombardment formulas showing how ions are generated depending on the desired elements. ⁵⁵⁾

$$ BF₃ + e⁻ → B⁺ + 3F + 2e⁻ \; (p-type \;dopant) $$ $$PH₃ + e⁻ → P⁺ + 3H + 2e⁻ \; (n-type \; dopant)$$ $$AsH₃ + e⁻ → As⁺ + 3H + 2e⁻ \; (n-type \;dopant) $$

This is usually done at room temperature in a vacuum environment.

This method uses high-temperature furnaces to drive dopants in gaseous and liquid forms into the surface of the wafer, with inert carrier gas transporting them. These dopants are typically composed of boron and phosphorus. ⁵⁶⁾

• Phosphorus (n-type)⁵⁷⁾: Phosphorus oxychloride (POCl3), Phosphine (PH3), Phosphorus pentoxide (P2O5)
• Boron (p-type): Boron nitride (BN), Diborane gas (B2H6), Boron Tribromide (BBr3)
• Nitrogen (N2) (carrier gas)
• Oxygen (O2) (Oxidizing gas)

• Phosphosilicate (PSG)
• Borosilicate (BSG)
• Cl2
• Br2

Gas phase decomposition for phosphorus oxychloride ⁵⁸⁾:

$$ 4 POCl₃ + 3 O₂ → 2 P₂O₅ + 6 Cl₂ $$ Followed by the doping with P : $$ 2 P₂O₅ + 5 Si → 4 P + 5 SiO₂ $$

Gas phase decomposition for Boron tribromide : $$ 4 BBr₃ + 3 O₂ → 2 B₂O₃ + 6 Br₂ $$ Followed by the doping with B : $$ 2 B₂O₃ + 3 Si → 4 B + 3 SiO₂ $$

The operating temperature of diffusion furnaces hovers around 800–1,200°C.

This process takes place after ion implantation and serves to recondition the semiconductor's crystal lattice. This is achieved by heating the material to a high temperature, which activates the recrystallisation process on the surface. ⁵⁹⁾

• Heat (900-1100°C)
• Inert atmosphere gases (N2) prevent oxydation of the surface

This method is a type of chemical vapour deposition (CVD), which involves doping the wafer surface using silicon-derived gases to form a crystalline thin film. The formation of the doped film on the wafer surface is referred to as epitaxy. ⁶⁰⁾ This is achieved by operating at high temperatures, depending on the favoured inputs and reactions.

• Silicon source gases: Silane (SiH4), Dichlorosilane(SiH2Cl2), Trichlorosilane (SiHCl3) ^{61) 62)}
• Phosphine (PH3) (n-type dopant gas)
• Diborane (B2H6) (p-type dopant gas)

• HCl
• Polysilicon deposits (etched away)

Silane pyrolysis ⁶³⁾

Silane pyrolysis $$ SiH₄ → Si (epitaxial) + 2 H₂ $$ Dichlorosilane - H2 reduction $$ SiH₂Cl₂ + H₂ → Si (epitaxial) + 2 HCl + H₂ $$ Trichlorosilane $$ SiHCl₃ + H₂ → Si (epitaxial) + 3 HCl $$ n-type doping : $$ PH₃ → P + 3/2 H₂ $$ p-type doping : $$ B₂H₆ → 2 B + 3 H₂ $$

• Diborane (B2H6)

• Applied Materials
• Axcelis
• Sumitomo Heavy Industries

• Applied Materials VIISta 900XP: Medium current ion implant
• Applied Materials VIISta 3000XP: Medium current ion implant
• Applied Materials VIISta 900 3D: Medium current ion implant / Advanced logic and memory: FinFET, 3D NAND and DRAM (<2Xnm)
• Applied Materials VIISta HCP: High current ion implant
• Applied Materials VIISta PLAD: PLAD
• Applied Materials VIISta Trident: High current ion implant / Advanced logic and memory (<2Xnm)
• Axcelis Purion H6 Series: High current ion implant
• Axcelis Purion XE Series: High energy ion implant
• Axcelis Purion M Series: Medium current ion implant
• Axcelis Purion H200 Series: Medium energy ion implant (high current) / Mature logic
• Sumitomo Saion: High to medium current ion implant / 200 to 300mm
• Sumitomo SHX III/S: High current ion implant / 300mm ; advanced logic and memory
• Sumitomo NV-GSDIII-180: High current ion implant / 100 to 200mm
• Sumitomo MC3-II-GP: Medium current ion implant / 200 to 300mm
• Applied Materials Producer Pyra Anneal: Annealing
• Applied Materials Vantage Astra DSA: Annealing
• Applied Materials Vantage RadOx RTP: Annealing, Rapid Thermal Processing (RTP)
• Applied Materials Vantage Radiance Plus RTP: Annealing, Rapid Thermal Processing (RTP)
• Applied Materials Vantage Vulcan RTP: Annealing, Rapid Thermal Processing (RTP)
• Applied Materials Centura DPN HD: Annealing, Decoupled Plasma Nitridation (DPN) / advanced logic and memory

• A CMOS integrated circuit with embedded memory may require more than 60 implant steps (Applied Materials).
• A large wafer fabricator may process up to 50,000 wafers/month, with each wafer requiring 20 to 30 implants. This output requires the use of about 20 implanters, each with the capacity to implant more than 200 wafers/h (Axcelis).Link

• Axcelis Purion H6 * High Current Ion Implanter

• Schroder, D. K. (2015). Semiconductor material and device characterization. John Wiley & Sons.
• Sadeghfar, F., & Ghaedi, M. (2021). Photocatalytic treatment of pollutants in aqueous media. In M. Ghaedi (Ed.), *Photocatalysis: Fundamental processes and applications * (Vol. 32, pp. 725–759). Elsevier. https://doi.org/10.1016/B978-0-12-818806-4.00011-5
• May, G. S., & Spanos, C. J. (2006). Fundamentals of semiconductor manufacturing and process control. John Wiley & Sons.
• Francis, T. A., Hasaka, S., Brabant, P. D., Torres, R. Jr., He, H., Reznicek, A., Adam, T. N., & Sadana, D. K. (2014). *Methods and apparatus for selective epitaxy of Si-containing materials and substitutionally doped crystalline Si-containing material * (U.S. Patent No. US8759200B2). U.S. Patent and Trademark Office. https://patents.google.com/patent/US8759200B2/en ([patents.google.com][1])
• Huet, K., Mazzamuto, F., Tabata, T., Toque-Tresonne, I., & Mori, Y. (2017). Doping of semiconductor devices by Laser Thermal Annealing. Materials Science in Semiconductor Processing, 62, 92-102.
• Qin, S., Hu, Y. J., & McTeer, A. (2012, May). PLAD (plasma doping) on 22nm technology node and beyond-evolutionary and/or revolutionary. In 2012 12th International Workshop on Junction Technology (pp. 1-11). IEEE.
• Raj, D. M., Godet, L., Chamberlain, N., Hadidi, K., Singh, V., & Papasouliotis, G. D. (2011, January). Optimization and Control of Plasma Doping Processes. In AIP Conference Proceedings (Vol. 1321, No. 1, pp. 142-145). American Institute of Physics.
• Gupta, A., Ray, A., Ameen, M., & Rzeszut, R. (2022). Introducing the Purion H200™ single wafer high current implanter: A. Gupta et al. MRS Advances, 7(36), 1295-1300. Link

• Silicon dioxide (SiO2)
• Silicon nitride (Si3N4)
• Polysilicon
• Tungsten (W)
• Nitrogen (N2)
• Hydrogen (H2)
• Hydrochloric acid (HCl)
• Silicon tetrachloride (SiCl4)

• Hafnium oxide (HfO2)
• Aluminium oxide (Al2O3)
• Zinc oxide (ZnO)
• Zircon oxide (ZrO2)
• Silicon oxide (SiO2)
• Yttrium oxide (Y2O3)
• Titanium tetrachloride (TiCl4)
• Zirconium (Zr)
• Titanium nitride (TiN)
• Tantalum nitride (TaN)
• Tungsten nitride (WN)
• Ruthenium (Ru)
• Oxygen (O2)
• Ammonia (NH3)

• Titanium (Ti)
• Tungsten (W)
• Tungsten-titanium (W-Ti)
• Aluminium (Al), including alloys
• Tantalum (Ta)
• Copper (Cu), including alloys
• Nickel-vanadium (Ni-V)
• Silicides

• To be defined

### Manufacturers

• Applied Materials
• LAM Research
• ASM International
• TEL

### Equipments

• LAM Altus Family: CVD (W) and ALD (WN, Mo) processes/ Advanced memory and logic: 3D NAND, DRAM, Interconnect, WN Barrier (via and metallizatio)
• LAM Coronus: Post-etch for shallow trench isolation, Pre and post deposition, Pre-lithography, Metal film removal, Wet and dry etch bevel protection / 3D NAND
• LAM Sabre Product Family: ECD (Cu) / Logic interconnect ; Memory interconnect
• LAM Sola Product Family: ultraviolet thermal processing (UVTP) / Low-k film treatment ; Strained nitride film treatment
• LAM Speed Product Family: High-Density Plasma Chemical Vapor Deposition (HDP-CVD) / Shallow trench isolation (STI) ; Pre-metal dielectrics (PMD) ; Inter-layer dielectrics (ILD) ; Inter-metal dielectrics (IMD) ; Passivation layers
• LAM Striker Product Family: Atomic Layer Deposition (ALD) / Gapfill dielectrics ; Conformal liners ; Patterning spacers and masks ; Hermetic encapsulation ; Etch stop layers ; Optical films
• LAM Vector Product Family: Plasma-Enhanced Chemical Vapor Deposition (PECVD) / Hardmask films ; Anti-reflective layers (ARLs) ; Passivation layers ; Diffusion barriers ; Multi-layer stack films for 3D NAND ; Core layers for double and quadruple patterning layers ; Inter-metal layers ; Global wafer stress management layers
• Applied Materials Producer XP Precision Pioneer CVD: CVD / Logic and DRAM
• Applied Materials Centura Ultima HDP CVD: Plasma CVD / 200 to 300mm
• Applied Materials Endura Volta Cobalt CVD: CVD for interconnect / advanced logic and memory
• Applied Materials Endura Volta Selective W CVD: CVD for gapfill/contact
• Applied Materials Endura Volta W CVD: CVD for gapfill/contact
• Applied Materials Producer XP Prcesion CVD: CVD for film deposition / advanced logic and memory
• Applied Materials Producer BLOk PECVD: PECVD for interconnect
• Applied Materials Producer Black Diamond PECVD: PECVD for dielectric film deposition / advanced logic and memory
• Applied Materials Producer CVD: CVD for film deposition
• Applied Materials Producer DARC PECVD: PECVD for film deposition / mature logic and memory
• Applied Materials Producer Eterna FCVD: FCVD for gapfill/contact
• Applied Materials Producer HARP: CVD for HAR/gapfill
• Applied Materials Producer Precision APF PECVD: PECVD for film deposition / advanced logic and memory
• Applied Materials Producer XP Precision Draco CVD: CVD for film deposition / DRAM
• Applied Materials Axcela PVD: PVD for sputtering
• Applied Materials Endura ALPS PVD (Co&Ni): Low-pressure PVD for metallization
• Applied Materials Endura Amber PVD: PVD for metallization
• Applied Materials Endura Avenir RF PVD: PVD for metallization / advanced logic
• Applied Materials Endura Cirrus HT Co PVD: PVD for metallization (Co) / DRAM
• Applied Materials Endura Cirrus HTX PVD: PVD for hard masks (TiN)
• Applied Materials Endura Clover MRAM PVD: PVD (MgO) / advanced memory (MRAM)
• Applied Materials Endura CuBS RF XT PVD: PVD (TaN/Ta/Cu)
• Applied Materials Endura iLB PVD/ALD: ALD (TiN)
• Applied Materials Endura Impulse PCRAM PVD: PVD / advanced memory (PCRAM, ReRAM)
• Applied Materials Endura Ioniq W PVD: PVD (W) / advanced logic and memory
• Applied Materials Endura PVD: PVD for metallization
• Applied Materials Versa XLR2 W PVD: PVD (W)

• Sarkar, J. (2010). Sputtering materials for VLSI and thin film devices. William Andrew.
• Schepis, D., & Seshan, K. (Eds.). (2024). Handbook of Thin Film Deposition: Theory, Technology and Semiconductor Applications. Elsevier.

• Silicon dioxide (SiO2)
• Aluminium oxide (Al2O3)
• Cerium oxide (CeO2)
• Deionized water (DI Water)
• Hydrofluoric acid (HF)
• Sulfuric acid (H2SO4)
• Sodium hydroxide (NaOH)
• Potassium hydroxide (KOH)
• Ammonium hydroxide(NH4OH)

• Applied Materials
• EBARA
• Hwatsing

• Applied Materials Opta CMP: metal and non-metal CMP; single-step batch and balanced/unbalanced multi-step sequential polishing; thick and thin film removal / advanced logic and memory (3D) <5nm
• Applied Materials Reflexion LK CMP: 300mm
• Applied Materials Reflexion LK Prime CMP: advanced logic and memory
• Ebara F-REX300XA: 300mm
• Ebara F-REX200M2: 200mm

• Ebara catalog
• Chemical Mechanical Planarization, CMP Process Fundamentals: CMP Tools and Process ; CMP Process Fundamentals: CMP Slurries

• Zantye, P. B., Kumar, A., & Sikder, A. K. (2004). Chemical mechanical planarization for microelectronics applications. Materials Science and Engineering: R: Reports, 45(3-6), 89-220.
• Seo, J. (2021). A review on chemical and mechanical phenomena at the wafer interface during chemical mechanical planarization. Journal of Materials Research, 36(1), 235-257.
• Seo, J., & Paik, U. (2016). Preparation and characterization of slurry for chemical mechanical planarization (CMP). In Advances in chemical mechanical planarization (CMP) (pp. 273-298). Woodhead Publishing.
• Kim, H. J. (2018). Abrasive for chemical mechanical polishing (pp. 183-201). Rijeka: InTech
• Lee, J., He, S., Song, G., & Hogan Jr, C. J. (2022). Size distribution monitoring for chemical mechanical polishing slurries: An intercomparison of electron microscopy, dynamic light scattering, and differential mobility analysis. Powder Technology, 396, 395-405.