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| intro_cmos [2026/06/26 17:50] – antoine | intro_cmos [2026/06/30 13:23] (current) – [Potential well] mathieu.ludden.ext |
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| ====== Complementary Metal-Oxide-Semiconductor (CMOS) Image Sensor ====== | ====== Complementary Metal-Oxide-Semiconductor (CMOS) Image Sensor (⚠️WORK IN PROGRESS⚠️) ====== |
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| ===== Definition ===== | ===== Definition ===== |
| </figure> | </figure> |
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| | <figure center |schema_cmos> |
| | {{ ::cmos_joli_schema.png?direct&400 |https://evidentscientific.com/en/microscope-resource/knowledge-hub/digital-imaging/cmosimagesensors}} |
| | <caption>CMOS Integrated Circuit Architecture [(Introduction_to_CMOS_Image_Sensors > [[https://evidentscientific.com/en/microscope-resource/knowledge-hub/digital-imaging/cmosimagesensors | Introduction to CMOS Image Sensors]])] </caption> |
| | </figure> |
| ===== Main components ===== | ===== Main components ===== |
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| ==== Microlens ==== | ==== Microlens ==== |
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| | A microlens array is a layer of tiny lenses positioned above the pixels of an image sensor. Each microlens is aligned with a single pixel and concentrates the incoming light onto the photodiode, which is the light-sensitive region of the pixel. |
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| | <figure center |microlens_array> |
| | {{ ::microlens-array.png?direct&400 |}} |
| | <caption> A microlens array [(https://micro.magnet.fsu.edu/primer/digitalimaging/concepts/microlensarray.html)] </caption> |
| | </figure> |
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| | <figure center|microlens_principle> |
| | {{ ::microlens_working_principle.png?direct&400 |}} |
| | <caption> Microlens array principle [(fabrication_microlens_array > [[https://link.springer.com/article/10.1186/s10033-018-0204-y |Yuan, W., Li, LH., Lee, WB. et al. Fabrication of Microlens Array and Its Application: A Review. Chin. J. Mech. Eng. 31, 16 (2018).]])] </caption> |
| | </figure> |
| ==== Color filter ==== | ==== Color filter ==== |
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| ==== Photodiode ==== | ==== Photodiode ==== |
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| It exists a lot of different types of photodiiode : n+/p-sub, n-well/p-sub, p+/n-well or p+/n-well/p-sub, pinned photodiode, buried photodiode, fully depleted pinned photodiode, vertical PIN, lateral PIN, deep-n-well PIN, spot PIN, stacked photodiodes, avalanche photodiodes, vertical color-separable PPDs, thin-film pinned photodiodes, and pinned photo-gates. | There is three types of vertical photodiodes suitable for fabrication in standard N-well CMOS processes : photodiodes using the N-well/P-sub, P<sup>+</sup>/N-well, and N<sup>+</sup>/P-sub junctions. |
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| The most-used type of pohtodiiode for CMOS is the pinned photodiiode. [(review_pinned_photodiiode > [[https://ieeexplore.ieee.org/document/6742594 | E. R. Fossum and D. B. Hondongwa, "A Review of the Pinned Photodiode for CCD and CMOS Image Sensors," in IEEE Journal of the Electron Devices Society, vol. 2, no. 3, pp. 33-43, May 2014]])] | |
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| ==== CMOS vertical photodiiodes types ==== | |
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| //This figure illustrates three types of vertical photodiodes suitable for fabrication in standard N-well CMOS processes : photodiodes using the N-well/P-sub, P<sup>+</sup>/N-well, and N<sup>+</sup>/P-sub junctions.// | |
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| <figure center |type_photodiiode> | <figure center |type_photodiiode> |
| {{ ::3_types_of_photodiiode_structure_and_1_phototransistor.png?direct&600 |https://www.mdpi.com/2079-9292/13/4/691#metrics}} | {{::photodiode_architecture.png?direct&400 |https://www.researchgate.net/publication/224460084_Which_Photodiode_to_Use_A_Comparison_of_CMOS-Compatible_Structures}} |
| <caption>3 types of photodiiode structure and 1 phototransistor [(A_Review_of_Optical_Sensors_in_CMOS)]</caption> | <caption>In order : (a) n<sup>+</sup>/p-sub, (b) n-well/p-sub, and (c) p<sup>+</sup>/n-well/p-sub [(wich_photodiode_to_use > [[https://www.researchgate.net/publication/224460084_Which_Photodiode_to_Use_A_Comparison_of_CMOS-Compatible_Structures/citation/download | Murari, Kartikeya & Etienne-Cummings, Ralph & Thakor, N.v & Cauwenberghs, Gert. (2009). Which Photodiode to Use: A Comparison of CMOS-Compatible Structures. Sensors Journal, IEEE.]])]</caption> |
| </figure> | </figure> |
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| * for 0.18 $\mu$m CMOS process : P<sup>+</sup>/N-well | * for 0.18 $\mu$m CMOS process : P<sup>+</sup>/N-well |
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| | The most-used type of photodiode for CMOS is the pinned photodiiode. [(review_pinned_photodiiode > [[https://ieeexplore.ieee.org/document/6742594 | E. R. Fossum and D. B. Hondongwa, "A Review of the Pinned Photodiode for CCD and CMOS Image Sensors," in IEEE Journal of the Electron Devices Society, vol. 2, no. 3, pp. 33-43, May 2014]])] |
| | The pinned photodiode has a p<sup>+</sup>/n-well/p-sub architecture, with a 4T pixel structure. |
| ==== Potential well==== | ==== Potential well==== |
| | The potential well in a CMOS image sensor is the electron storage region formed inside the N-type pinned photodiode. The combination of the N photodiode and the shallow P+ pinning layer creates a controlled electrostatic minimum that stores photoelectrons with low noise and allows efficient transfer during readout. This structure is the foundation of essentially all modern CMOS image sensors. |
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| | The potential well will determine key sensor of the CMOS image sensor such as the Full Well Capacity (FWC), the Charge Transfer Efficiency (CTE), the dark current, the dynamic range, etc.[(Measurement_of_charge_transfer_potential_barrier_in_pinned_photodiode_CMOS_image_sensors > [[https://www.jos.ac.cn/article/doi/10.1088/1674-4926/37/5/054007 | Chen Cao, Bing Zhang, Junfeng Wang and Longsheng Wu Measurement of charge transfer potential barrier in pinned photodiode CMOSimage sensors 2016]])] |
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| ===== Working Principle ===== | ===== Working Principle ===== |