3D DRAM manufacturing
Process flow for 3D devices on DRAM
Xiao1) provides the most detailed description of the processes used to manufacture 3D DRAM and NAND devices. Such a detailed public explanation is rare to find and applies only to two types of devices for advanced technology nodes. Nevertheless, it provides a detailed understanding of the various process loops for each mask.
AA Module
- Wafer clean
- Pad oxidation
- SiN hard mask deposition
- Amorphous silicon hard mask deposition
- AA mask 1
- Etch top hard mask
- PR strip/clean
- AA mask 2
- Etch bottom hard mask
- PR strip and clean
- Etch pad oxide
- Etch silicon trench
- Wafer clean
- Oxidation
- STI oxide CVD to fill the trench
- STI oxide CMP, stop on nitride
- Wet strip nitride and pad oxide
- Wafer clean
Well formation
- Sacrificial oxide growth
- Cell p-well mask
- P-well implantation
- N + S/D implantation
- PR removal and clean
- Peripheral n-well mask
- N-well implantation
- PMOS VT adjust implantation
- PR removal and clean
- Peripheral p-well mask
- P-well implantation
- NMOS VT adjust implantation
- Photoresist removal and clean
- Sacrificial oxide removal and clean
- Rapid thermal anneal
BWL module
- Wafer clean
- Oxidation
- Hard-mask deposition
- BWL mask
- Etch hard mask
- BWL trench etch
- PR strip & clean
- Oxidation
- W and TiN etch back
- Wafer clean
- Oxide deposition
- Oxide CMP
- Strip hard-mask
- Oxide deposition
- TiN gate electrode deposition
- W deposition
BLC module
- Wafer clean
- Peripheral mask
- Etch oxide
- PR strip/clean
- Gate oxidation and nitridation
- Polysilicon deposition
- Wafer clean
- PMOS poly-dope mask
- PMOS poly implantation
- PR strip/clean
- Array area mask
- Etch polysilicon
- PR strip/clean
- BLC mask
- Etch oxide
- PR strip clean
- Polysilicon deposition
- TiN and W deposition
- SiN deposition
BL and peripheral transistor module
- Wafer clean
- BL mask
- BL and peripheral gate etch
- PR strip/clean/ACI
- Re-oxidation
- Peripheral NMOS SDE mask
- Peripheral NMOS SDE implantation
- PR strip/clean
- Peripheral PMOS SDE mask
- Peripheral PMOS SDE implantation
- PR strip/clean
- Spacer dielectric film deposition
- Spacer film etch back
- Peripheral NMOS SD mask
- Peripheral NMOS SD implantation
- PR strip/clean
- Peripheral PMOS SD mask
- Peripheral PMOS SD implantation
- PR strip/clean
- RTA
SNC, peripheral contact, and M1 process steps
- ILD1 deposition
- LD1 CMP
- HM deposition
- SNC mask 1
- Etch HM
- PR strip/clean
- SNC mask 2
- Etch HM
- PR strip/clean
- Etch ILD1
- Wafer clean
- Ti/TiN/W deposition
- W/TiN/Ti CMP
- Etch stop layer deposition
- ILD2 deposition
- M1 mask
- Etch ILD2
- PR strip/clean
- Ti/TiN/W deposition
- W/TiN/Ti CMP
SN module
- Wafer clean
- Each stop layer (ESL) deposition
- ILD deposition
- SiN deposition
- SN mask 1
- Etch nitride
- PR strip/clean
- SN mask 2
- Etch nitride
- PR strip/clean
- Etch oxide
- TiN deposition
- PR coating
- RP etch back
- TiN etch
- SiN slot mask
- Nitride etch
- PR strip/clean
- ILD removal
- Wafer clean
- High-k film deposition
- TiN and conducting filler deposition
V1 and M2 process steps
- Peripheral area mask
- Etch SiGe/TiN/ZAZ
- PR strip/clean
- ILD3 deposition
- ILD3 CMP
- V1 mask
- V1 etch
- PR strip and clean
- Ti/TiN deposition
- W deposition
- W/TiN/Ti CMP
- ESL deposition
- ILD4 deposition
- M2 mask
- M2 etch
- PR strip and clean
- Barrier and seed-layer deposition
- Bulk copper plating
- Cu anneal
- Cu CMP
V2 and M3 process steps
- ESL, ILD5, and dielectric cap deposition
- Metal HM deposition
- M3 mask
- HM etch
- PR strip and clean
- V2 mask
- Dielectric cap and ILD5 etch
- PR strip and clean
- ILD 5 etch
- ESL removal
- Clean
- Barrier and seed-layer deposition
- Bulk copper plating
- Cu anneal
- Cu CMP
V3-M4 and passivation process steps
- ESL and ILD6 deposition
- V3 mask
- ILD6 and ESL etch
- Pr strip and clean
- Ti/TiN/W deposition
- W/TiN/Ti CMP
- Wafer clean
- Ti/Al-Cu/TiN deposition
- M4 mask
- Etch TiN/Al-Cu/Ti stack
- PR strip and clean
- Passivation oxide and nitride deposition
- Bond pad mask
- Etch nitride and oxide
- PR strip and clean
1)
Xiao, H. (2016). 3D IC Devices, Technologies, and Manufacturing. SPIE press.
Discussion